Verification Tests
The wave solder joint appearance was qualified per IPC-610D wherever solder joints could be
visually inspected. The purpose of this inspection was to detect the solder quality by visual
assessment, e.g. bridging, insufficients, misalignment, opens etc… For the wave test vehicles,
visual inspection was used to detect bridged pins, excess solder balls, missing components,
opens, off-alignment (backside SMT components), etc… before X-ray inspection. For all first pass
and reworked test boards, there should be no visual defects based on IPC standard IPC-A-610D.
Voids are created from various sources such as flux, unclean surfaces, temperature and moisture.
The surface tension is higher for Pb-free SnAgCu alloys than SnPb. Regardless of pin to hole area
ratio, if a component pin is too close to the board barrel wall, voids will connect to both pin and
barrel surfaces. Rough surfaces are more difficult for voids to break free from and have more
surface area. Other factors contributing to voids not escaping the wave soldered joint include the
fact that the SnAgCu alloy pot temperature is closer to solidification temperature than SnPb,
thereby allowing less time for a void to escape. All parameters being equal, larger holes with low
pin to hole area ratios have less voids.
The final assembled boards were submitted to the regional materials characterization lab for
evaluation. Pull testing was done to provide information on mechanical strength for LF wave
soldered joints on SOIC devices. Cross-sectional analysis was used to check the solder joint
wetting, metallurgical bonds and failure mode of solder joints. A detailed assembly report is
submitted to the regional materials characterization lab and Corporate ECT RoHS qualification
group. The regional FA lab performs the pull tests and cross-sections for required components, and
combines their analysis report with the assembly report and submits to the Corporate ECT RoHS
qualification group for final approval based on benchmarking corporate developed data.
This process was used for every Solectron PCB manufacturing site around the world. Since the EU
directives and regulatory requirements of RoHS are continually evolving, site and regional RoHS
leaders must pay full attention to the ECT for any updates and additional requirements. This
deployment process gives us a vehicle for getting valuable data and information to the sites for
their readiness in the upcoming months of transition for lead-free/RoHS compliancy. The
development teams also have valuable contacts at each of the sites with regard to any new
discoveries.
Acknowledgements
Solectron would like to gratefully acknowledge the contributions of the following: the members of
the Solectron Design and Engineering Process Development teams in Charlotte, Austin,
Milpitas/Fremont and Singapore for the upfront development work. The cooperation of Solectron
Operation’s engineering teams in Penang, Scotland, France, Germany, Texas, China,
Milpitas/Fremont and Mexico, for their work in completing the qualification activities. |
