5.1.4   Component placement and routing of tracks

The most noisy or susceptible components in each area should be positioned first, as close to the centre of their areas and as far away from cables or wires as possible. Such components include clock generators and distribution (extremely noisy); bussed digital ICs (very noisy); microcontrollers (noisy); switch-mode power transistors and rectifiers and their chokes, transformers, and heatsinks (all very noisy), analogue ICs (sensitive), and millivolt level amplifiers (very sensitive). Remember (from Part 1) that even low-frequency operational amplifiers can be extremely susceptible to interference, even beyond 1GHz.

After the extremely short connections from components to reference planes, digital clock distributions (very aggressive signals) must be the next "nets" to be routed, and must be run on a single PCB layer adjacent to a  0V plane. These tracks must be as short as possible, and even so may need to use transmission-line techniques (described later). It may be necessary to experiment with component placement to achieve minimum track lengths. Where clock tracks are made longer than necessary to minimise skew, a "serpentine" layout is best.

Digital busses and high-speed I/O should be routed next, in a similar manner to clock tracks, deferring only to clock tracks and plane bonds where there is a conflict. Very susceptible tracks, such as those carrying millivolt transducer signals, should also be routed as if they were clock or data buss tracks, although they will always be in a different segregated area of the PCB. The later section on transmission lines describes what to do where critical tracks have to change layers.

All other types of analogue, digital, and power signals should also be routed according to how aggressive or sensitive they are. Where these characteristics are not obvious from a circuit analysis, probing a prototype with a wide-band oscilloscope (and/or spectrum analyser) with voltage or current probes will reveal which are the most aggressive, and injecting voltages or currents from a wideband sweep generator will reveal which are most sensitive. A loop probe can be most useful here, being able to inject signals into tracks without requiring connection of external equipment to potentially sensitive area of the circuit concerned.

All components and their tracks must be contained within their designated PCB areas. The only tracks to exit or enter an area are those that have to connect to other areas. If it has not proved possible to eliminate all the wires and cables inside a product, make sure that their routes are fixed so they can’t stray into the wrong PCB areas.

It is best to check that segregation instructions have been followed on draft PCB layouts, well before PCB manufacture. An easy check is to count the tracks and other conductors which cross the dotted lines showing the segregated areas on the circuit diagram – there should be exactly the same number crossing the channels between areas on the draft PCB layout. Where PCBs have been autorouted it is usual to find additional tracks crossing area boundaries – these are often the source of much design heartache, so eliminate them right away by applying more skill to the track layout. Autorouting does not generally provide good layouts for EMC purposes.

5.2 Interface Suppression

EM disturbances can be radiated and/or conducted across interfaces between segregated areas, and shielding, filtering, or isolation techniques (such as opto-coupling) are used to reduce this to acceptable levels. To decide on the most cost-effective methods for each interface, they should be assessed for all the EM phenomena possible, given the operational EM environment and the emissions/immunity characteristics of the circuits concerned.

Don’t ignore internal power supplies and other common connections such as 0Vs or grounds when considering interfaces between areas. Circuit designers abbreviate such connections on their circuit diagrams, often to invisibility, even though they provide the return current paths that are as important as the send path.

5.2.1 Suppressing outside/inside-world  interfaces

Conductors passing from outside to inside-worlds may need the full range of suppression techniques – shielding, filters, isolating transformers, opto-isolators, surge protection devices, etc. As described above, best practice is to use a single PCB area or panel in the enclosure shield for all outside/inside-world interconnections and their suppression.

Visual displays (such as LCDs, LEDs, VDUs, moving-coil meters, etc.) and controls (such as pushbuttons, potentiometers, rotary knobs, etc.) are also interfaces between outside and inside-worlds, and are particularly exposed to personnel electro-static discharge (ESD), which will be covered by Part 6 of this series.

Shielding (See Part 4) may be applied to chips or areas of the PCB; the whole PCB; sub-assemblies of PCBs; entire assemblies of PCBs; or the entire product (listed in ascending order of cost and difficulty). The segregation methods described above help make low-cost shielding possible.

5.2.2 Interfaces between dirty/high speed/noisy and clean/sensitive/quiet areas

Determining the types/amounts of suppression to be applied to tracks and other conductors interconnecting different PCB areas needs an assessment of both the desired signals and the unwanted noise they may carry, plus the sensitivity of the circuits they connect to.

Digital clocks and data busses are aggressively noisy and should not be allowed in clean/sensitive/quiet PCB areas. Data intended for a sensitive area should be latched from its bus no closer than the boundary of that area, and the data busses themselves restricted to a noisier area.

Power distribution networks are often overlooked routes for conducted noise from one segregated area to another, as are "static" data lines, and other low-frequency signals. Digital control lines which remaining at logic 1 or 0 for long periods are often thought to be quiet, but they usually carry tens or even hundreds of millivolts of high-frequency noise generated by the electrical activity of their source ICs (e.g. by “ground bounce” and its corresponding “power bounce”). Many an analogue circuit has suffered from noise on its power supply rails from switch-mode power supplies or DC/DC converters, or from digital processing sharing the same rails or from noise injected into analogue switches and opamps from “static” logic control signals. It is often necessary to fit small filters to such inter-area connections, but sometimes more drastic measures are required, such as opto-isolation.

Components that interface between segregated areas, such as analogue-to-digital convertors, transformers, data bus latches, filters, isolators, and the like, should be positioned at an edge  common to the areas they interconnect. They should usually remain wholly within one area or the other (so as to keep a component-free channel) and their tracks must route directly to their respective areas and not mingle with tracks associated with the “other side” of these components or other areas. The purpose of keeping the channel component-free is to make it easier to fit shielding over the segregated areas of circuitry, should it be needed. Where interface components like ferrite beads, common-mode chokes, or opto-isolators are placed in one of these channels it can help to achieve good separation between the tracks associated with each circuit area, but the cut-outs they require in any PCB-mounted shield may compromise its shielding effectiveness.

This compromise between the need for good track segregation and for shielding effectiveness does not apply when ‘feedthrough’ filter components are fitted as interconnections between segregated areas. These are designed to fit into and actually penetrate the walls of screened enclosures, so when fitted in (otherwise component- and track-free channels) they encourage good track segregation and don’t compromise shielding effectiveness. Traditionally, feedthrough filters are screwed or soldered into a hole in the shield, with wires connecting to their ends. This does not suit robotic surface-mounted assembly techniques, prompting some manufacturers to produce ‘SMD feedthrough filters’. These generally have an earth electrode around their centre, which is intended to be soldered to the PCB reference plane (although some types may also be able to be hand-soldered to a cut-out in their shield). In general the small size and low-profile of these parts means that they only require a very small cut-out in the shield they penetrate, and so may be expected to have little effect on shielding effectiveness. Where SMD ‘feedthroughs’ are used, their performance will be improved if the shield they are associated with is soldered to the PCB reference plane as close as possible to the SMD feedthroughs, as frequently as can be achieved. Very stringent applications sometimes require PCB shields to be seam-soldered all around their circumference, and such assemblies would probably need to use the more traditional wired-in feedthrough devices.

Radiated interference between segregated areas is possible. The stray capacitance between components may only be a fraction of a pF, but at high frequencies can inject significant  displacement currents into components and tracks in neighbouring areas. Combining small-sized low-profile components with PCB reference planes, and placing the noisiest devices (e.g. clocks, processors, switch-mode power devices) and signals in the centres of their areas, can help avoid the need to shield PCB areas from each other.

5.2.3 Details of interface suppression techniques

Suppression techniques include:

·         common-mode and/or differential mode filtering

·         galvanic isolation using opto-isolators or transformers

·         communications protocols (to improve bit error rate in the presence of interference)

·         surge protection devices

·         the use of balanced drive and receive signals (instead of "single ended")

·         the use of fibre-optic, infra-red, wireless, laser, or microwave instead of copper cables

·         shielding of areas, volumes, cables, and connectors

All of these are covered by other parts of this series. It is important to realise that on a PCB only a plane (described next) can provide a good enough reference at high frequencies to enable the full performance of filters, cable screens, and internal shields to be achieved on a PCB.

5.3 Reference planes

Due to their intrinsic reactance and resonances, tracks, wires, “star grounding”, area fills, guard rings, etc., cannot provide an adequate reference for a PCB except at low frequencies (usually below 1MHz).  For example, the rule-of-thumb for the inductance of PCB tracks on their own or single wires, is 1nH/mm. This means that just 10mm of PCB track has an impedance of 6.3 W at 100MHz, and 63W at 1GHz. For this reason, only unbroken areas of metal conductor can provide an adequate reference up to 1GHz (and beyond), and these are called reference planes. In a PCB these are usually called power, ground, or 0V planes, but it is best to avoid the use of the words “ground” or “earth” in connection with EMC and circuits (reserving them for specific uses associated with safety bonding). As far as most EMC design techniques are concerned, a connection to the green/yellow protective earth conductor can often be more of a problem than a solution.

Reference plane techniques allow dramatic reductions in all unwanted EM coupling when used in conjunction with the other techniques described here. Reference planes are also essential for almost every other PCB EMC design technique to function properly.

5.3.1 Creating proper reference planes

A high-quality high-frequency reference must have a vanishingly small partial inductance, and can be created on a PCB by devoting one layer to an unbroken copper sheet, called a reference plane. A 0V reference plane would be used as the 0V (or “ground”) connection for all its associated circuits, so that all 0V return currents flow in the plane and not in tracks. Power planes are created and used in a similar manner for power connections and their return currents.

0V reference planes must lie under all their components and all their associated tracks, and extend a significant distance way beyond them. The segregation and interface suppression techniques described above must still be followed even where a common 0V plane is used for a number of circuit areas.

Perforations such as leads, pins, and via holes increase the inductance of a plane, making it less effective at higher frequencies. “Buried via” techniques have been developed for cellphones, allowing interconnections between tracking layers without perforating the reference plane. For less demanding products a rule-of-thumb is that any gaps must have dimensions of 0.01l or less at the maximum frequency concerned. For a good plane at 1GHz, (e.g. to help meet most of the present EU harmonised EMC standards cost-effectively) this rule implies that plane gaps should have dimensions £ 1.5mm (remembering that the velocity of propagation in FR4 is approx. half of what it is in air). "Sneaking" tracks into a plane layer is not allowed.

Unavoidable gaps in a plane must not merge to create larger ones. PCB design rules should size clearance holes so that for regular hole spacings such as DIL packages, the plane "webs" between holes as shown by Figure 5B.

Tracks, area fills, guard rings, etc. forming part of the reference on signal layers can be used to good effect at high frequencies – but only when bonded to an underlying 0V plane with at least one via hole every 5 to15mm (using a random allocation of spacings).

0V planes should extend well beyond all components, tracks and power planes. [1] recommends “the 20H rule”: 0V planes should extend by at least 20 times their layer spacing. High-speed components (such as digital clocks, processors, and memory) and their signal tracks should always be placed near the centres of their segregated areas, well away from plane edges.

All 0V and power connections must bond immediately to their respective planes to minimise their connection inductance. Leaded components must have their through-plated holes directly connected to planes using thermal-break pads as shown by figure 5B (sometimes called wagon-wheels) to help with soldering.  Surface mounted devices (SMDs) for reflow soldering have to compromise the prevention of dry joints or “tomb-stoning” with the need to minimise inductance of plane connections.

Figure 5C shows various methods for connecting reflow-soldered SMDs to planes. Best is to use over-sized pads, tenting the solder-resist over a number of plane vias. Plane connections that do not need to be soldered (typical of the vias for reflow-soldered SMD components) may not need to use thermal-break pads – and using solid plane connections instead will reduce inductance.

It is best to make reference planes rectangular (but not thin) to minimise their partial inductance, and also to make the fitting of PCB level shielding easier. Square planes, and planes with simple aspect ratios such as 1:2, should be avoided to help reduce possible problems with resonances. Where there are a number of different power supplies, there may need to be a number of different power planes. Segregation of circuit areas (see earlier) makes it easier to fit several broadly rectangular power planes on the same layer.