5.3.2 Connecting 0V planes to chassis
Components and tracks have weak capacitive coupling to everything else. Electrical activity causes displacement currents to flow in these “stray” capacitances, a cause of common-mode emissions. High-speed circuits usually need at least a nearby metal surface, and (increasingly) a fully shielded enclosure, to reduce the resulting emissions problems. The metal chassis or shields need to be connected to the reference plane of their PCB, preferably at a number of points spread over the PCB so that the high frequency displacement currents can be returned to their source within a fraction of their wavelength. PCB mechanical supports and fixings are often used for these chassis bonds, but should be very short (< 4mm). There should be at least one bond in the centre of each area of high-speed circuitry, especially clock generators and distribution. For high-speed digital boards, 0Vplane to chassis bonds every 50 to 100mm all over the PCB may not be overkill, and provision (at least) should be made for these on prototype PCBs. Even if it is not intended to have a metal chassis or shielded enclosure, it is still a good idea to include a number of potential chassis bonding points, just in case. Sometimes a sheet of aluminised cardboard or PVC is sufficient to overcome unexpected problems, providing it can be bonded to the right place(s).
To add flexibility, especially for mixed analogue/digital PCBs, each plane-to-chassis bond can have tracks and pads that allow the bond to be left open, or else fitted with direct links or capacitors of various types and values. Fitting a direct link at one chassis bond and capacitors at the others allows low frequencies (for which the inductance is not important) to be controlled with a “star ground” system, whilst high frequencies are controlled by the low inductance of the widely distributed capacitive links. Care should be taken to minimise the inductances of all these tracks, pads, and linking components (SMD preferred). Where reference planes must be galvanically isolated only capacitor bonds may be used, but care should be taken with safety approvals and earth-leakage requirements (especially for patient-coupled medical apparatus).
5.3.3 Shielding effect of planes
Antennas placed close to metal planes are less effective at radiating and receiving. Many advantages of planes are due to the way they allow the return currents to take the path of least inductance, but their “antenna shielding” effect is also important. For any significant advantage to be achieved from this effect, the tops of all the PCB components must be no more than one-twentieth of a wavelength above a PCB plane, at the highest frequency of concern for emissions and immunity, e.g. 15mm to give a degree of shielding to analogue circuits exposed to 1GHz immunity testing.
Even lower profiles will give improved shielding, one reason why SMD components are much preferred for EMC, with very low profile ball-grid-array and flip-chip technologies being better still. The plane needs to extend by considerably more distance around the components than their height above it.
5.3.4 Interconnecting planes in multi-PCB assemblies
Card cage, backplane, and mother/daughterboard structures will experience considerable signal integrity and EMC advantages from linking their reference planes together with very low inductance. This may be achieved with frequent low-inductance links between their planes, more-or-less uniformly distributed along the full length of all their common boundaries. Shielded backplane connectors are happily becoming more commonly available. Where shielded connectors aren’t used, using one 0V plane-linking pin alongside every signal or power pin in a connector may seem expensive, but sometimes it is the lowest-cost (or only practical) way to improve the EMC of a multiple-PCB product. Bonding planes via front panels and/or card guides is also very worthwhile.
5.3.5 To split or not to split?
Split reference planes may give better or worse EMC (and signal integrity) than unsplit planes, and this depends very much on the PCB layout and circuit design so it is often hard to decide which method to use. Note that where a 0V plane is to be split off from the main 0V plane, it may still need chassis bonds as described earlier. This is particularly true of “traditional” method of splitting off connector panel 0V plane areas (to try stop noise on the main board from exiting via the external connectors), when the connector area on the PCB must have its local 0V plane bonded to any enclosure shielding. Also note that the inevitable stray capacitance across a split progressively “shorts it out” above 500MHz anyway.
To get any benefits from split planes with modern electronic technologies requires significant attention to detail, which is one reason why an increasing number of designers are now using common, unsplit 0V planes as a matter of course.
Allow for both split and unsplit options, on prototype PCBs at least, by splitting all planes at the natural boundaries between the segregated circuit areas, but also providing the means to "stitch" them together manually later on. Stitching requires pairs of via holes on each side of the split every 10mm or so (random spacing of 5 to 15mm preferred). These via pairs may be left open, or bridged with short wires or capacitors, and it is important to pitch the via pairs close together so that small capacitors or "zero-ohm links" can be used (preferably SMD). Linking planes with a single copper link and multiple capacitors can control lower frequencies (where inductance is not significant) by "star grounding", whilst also controlling higher frequencies by creating the effect of a single low-inductance plane.
Because a split in a plane is a slot antenna, it is best if no tracks cross the split (or even go near to it). Where tracks have to cross – they must have carefully-defined return current paths, and for high frequency currents these paths must be physically adjacent to their send tracks. These tend to defeat the purpose of the split, so should be limited to the bandwidth of the wanted signal (which should already have been restricted to just what is needed, as described in the section on interface analysis and suppression above). High-speed signals can usually be returned through a suitable size and type of capacitor, although some data streams with highly-variable content may need a more wideband return path than a single capacitor can easily provide (may need a direct link).
Balanced signals would ideally need no local return path, but in practice their balance always degrades at some frequency so a nearby return path is needed for the resulting common-mode “leakage” (usually a small-value capacitor). DC power and low-frequency signals that have been filtered to remove all high-frequency noises can use the star point between the split 0Vs for their return, as long as the inductance of the resulting current loop is negligible. Beware of assuming that a conductor is only carrying low frequencies just because that is what its signal name implies. In modern mixed digital/analogue products all the tracks and other conductors in a product usually carry significant levels of high frequency noise. A local return path for a low-frequency signal could be a ferrite bead.
Common-mode (CM) chokes fitted to any types of signals and their associated returns (e.g. a 4-circuit CM choke for a set of three related signals and their return) will probably help get the best performance from split planes, but cost more.
When all the above has been designed into the split-plane PCB, it will need testing and optimisation. Direct or capacitive links to/from the “stitching vias” should be added/subtracted to achieve the best EMC performance. If it is discovered that the best EMC is achieved when all the stitching points are directly linked, the next iteration of the PCB could remove the splits and their stitching points completely, saving manufacturing costs.
5.3.6 Galvanically isolated planes
The split planes described above are all ultimately powered from the same power rails (0V, at least), so there is a clear need for return current paths to be catered for every conductor (signal or power) that crosses from one plane area to another. It is often assumed that galvanically isolated areas have no return current requirements, but this is not so at high frequencies.
Galvanic isolation devices (opto-isolators, transformers, etc.) suffer from stray internal capacitance. A typical opto has 0.8pF internal capacitance, which provides a shunting impedance of only 2kW at 100MHz, or 200W at 1GHz, which will clearly prevent signal isolation from being maintained at high frequencies. Transformers (especially in DC/DC power converters) tend to have even larger stray internal capacitances. Common-mode chokes may be used to improve the isolation at high frequencies, but struggle to increase it by an order of magnitude at 1GHz. There are also many other stray capacitances around to compromise isolation. So there is a need, at high frequencies, to provide a local return path for the displacement currents that flow in these stray capacitances, to prevent them from causing common-mode conducted and radiated emissions and immunity problems.
Because we usually only need isolation for low frequencies (usually only 50Hz) we can connect galvanically isolated planes to the main reference plane with a number of low-value capacitors (spread around the gap perimeter), so as to achieve the effect of a single reference plane for high frequencies and provide low-inductance local return paths for stray displacement currents.
Of course, great care may need to be taken with component approvals and leakage currents where safety is concerned.
5.3.7 What if multilayer PCBs are thought too costly?
In volume, four-layer PCBs now only cost between 20% and 50% more than two-layer. The use of planes usually turns out, in retrospect, to have been the most cost-effective EMC technique possible, especially when the overall financial break-even time and profitability of a product is considered.
An appropriate technique for low-density double-sided PCBs is to put all the tracks on one side, and a solid 0V plane on the other. For digital products, the lack of a power plane might require a number of ferrite beads in the power rails (see later), so it might not prove to be most cost-effective.
Where tracks must use both sides of a two-layer PCB, some EMC improvements may be had by "gridding" 0V tracks. This can be done by using a "maximum copper" or "area fill" on the 0V tracks of both PCB layers, which must run perpendicular to each other, "stitching" the resulting horizontal and vertical 0V areas and lines together with via holes wherever they cross to create a grid over the whole PCB area. Smaller grid sections are needed around the more sensitive or aggressive components, often difficult to achieve for leaded microprocessors but easier for SMD types. Time should be allowed for moving components and tracks around to achieve the best grid structure, but any grid will always be much less effective than a proper solid plane.
Single-sided PCBs are extremely difficult to make EMC compliant without enclosure shielding and filtering, except for circuits which naturally have very low emissions (low dV/dt and dI/dt) and also have naturally very high immunity (e.g. high signal levels and low impedances).
5.4 Power decoupling
The aim of power decoupling is to maintain the power supply impedance to each IC at 1W or less across the entire frequency range of interest (at least 150kHz to 1GHz for EMC). Some devices may need 0.1W or less over some frequency ranges for correct operation. Wires and PCB tracks have too much inductance to provide these low impedances, which require local capacitance of suitable quality and great attention to detail in PCB layout to minimise inductances.
Another aim is to reduce the size of the current loops in the power distribution, to reduce the emissions form this source. Happily, this is accomplished by the same techniques that lower the power supply impedance.
5.4.1 Power decoupling techniques
A large decoupling capacitor (typically 100mF, might be larger for power-hungry circuits) should be fitted where power supplies enter or leave a PCB, and some smaller ones (e.g. 10mF) should be ‘sprinkled’ around the PCB on a "mF per unit area" principle, as well as being positioned near to heavy power usage such as microprocessors, memory, and other powerful digital ICs. Using electrolytic technology these ‘bulk’ capacitors can provide a low impedance to about 3MHz.
Recently, several manufacturers have added high-capacitance multilayer ceramic capacitors to their surface-mounted product ranges. These are smaller or less costly or have lower ESR and/or better high frequency performance than electrolytics (such as solid tantalum), often several of these attributes at once. They also don’t suffer from reverse polarity or dV/dt problems, so should improve yields and reliability).
Next, the power supplies to every IC should be decoupled very nearby using appropriate capacitor sizes and types. Where an IC has a number of power pins, each pin should have an appropriate decoupling capacitor nearby, even if they are on the same supply (e.g. Vdd).
Achieving good decoupling above 10MHz gets more difficult as frequency increases, because the inductance of component leads, PCB tracks, via holes, and capacitor self-inductance, inevitably limit their performance. The achievement of good power supply decoupling at higher frequencies using capacitors mounted close to IC power pins is discussed next.
The total local decoupling capacitance required depends on the IC’s transient power demands and the tolerances of its DC power rails. VLSI and RAM manufacturers should be able to specify the values (and maybe even the capacitor types and preferred layout patterns) for their products, but note that they will probably have assumed an accurate 5V power supply – usually not true of real life.
The formula C(DV) = I(Dt), using the units Farads, Volts, Amps, and seconds, covers what we want to know. DV is obtained by subtracting the IC's minimum operational voltage (from its data sheet) from the worst-case minimum power rail voltage (taking account of initial tolerances, regulation, temperature coefficients, ageing drift, and the voltage drops in the power conductors). DV often turns out to be a mere +100mV. I is the IC's transient current demand from its power rail, which lasts for Dt. I and Dt are almost never found in data sheets, and must be measured in some reasonably sensible way with an oscilloscope. An obvious component of I is the device’s output (load) current, but this is often negligible in comparison with “shoot-through" currents, also known as “transient supply current”. There is no point in measuring I or Dt with greater than ±20% accuracy.
Where DV is low it may be cost-effective to increase it by improving the regulation of the power supply, and/or reducing the resistance of the power rails, rather than fit larger capacitors with their lower performance at high frequencies. This is a common argument for local power regulation.
5.4.2 Self-resonance problems
Self-resonance in capacitors stops them providing low impedances at high frequencies, with higher values generally being worse. The fir st self-resonant frequency (SRF) of a capacitor is a series resonance, and a rule of thumb for this is:, where L = ESL (internal to the capacitor) + the total inductance of any leads + the total inductance of any tracks and/or vias. 1nH/mm may be assumed for leads and/or tracks from a capacitor to the power pins of its IC. The inductance contributed by 0V and power planes may be neglected when the capacitor is near to its IC. Decoupling capacitors generally become ineffective at more than 3 times their SRF, as shown by Figure 5D.
It is interesting to note that the favourite 100nF capacitor, even with no tracks at all, is effectively useless above 50MHz, yet it is still often seen in circuits with clocks of 50MHz or over, where it can do nothing to help control the fundamental clock frequency, never mind its harmonics.
Close proximity of adjacent 0V and power planes (with their low internal and connection inductances) can provide capacitance with no SRF below 1GHz. Two planes separated by 0.15mm in an FR4 PCB achieve approximately 23pF/sq.cm of high quality RF capacitor. Good decoupling from 10 to 1000MHz can be achieved by combining adjacent 0V and power planes with SMD ceramic capacitors (COG and NPO types are best). Sometimes two different values of capacitors (e.g. 100nF and 1nF) may be required. Low inductance bonds from IC power pins and decoupling capacitors to their planes is essential, and the capacitors must be positioned close to their IC. The common practice of tracking from IC power pin to decoupling capacitor, and only then connecting to the plane, does not make best use of plane capacitance.
Whenever two capacitors are connected in parallel, a high-Q (i.e. sharp) high impedance resonance is created which could compromise power impedance at that frequency. This is easily dealt with on PCBs which have a dozen or more decoupling capacitors, since for every sharp high-Z resonance there are a number of alternate current paths with low-Z, which will swamp it. It may be a good idea to fit decoupling capacitors of 10 to 100nF in large areas of planes which are devoid of ICs, to help this swamping process. Parallel resonances are very sharp and often don’t correspond to any harmonics so have no effect, but unless it is known that this will also be the case for a new PCB (and that no-one will ever alter its clock frequencies) it is risky to ignore their potential for upset.
Parallel resonance problems are more likely to occur where only a few decoupling capacitors are used, for example where a small circuit area is powered from a dedicated power plane. It may be controlled by fitting a low-value resistor (say 1W) or small ferrite bead (preferably using SMD packages and short tracks) in series with one lead of the larger value capacitors. Alternatively, adding a number of additional capacitors with differing values should help. |
