The sudden change in characteristic impedance at the edges of parallel PCB planes creates resonances at integer multiples of half-wavelengths. For example, the first such resonance for a 150mm width or length would be around 500MHz for a bare PCB, moving down in frequency as the PCB was loaded with decoupling capacitors (which slows the velocity of propagation in the planes). This was the reason for recommending non-square rectangular plane shapes (and non-simple aspect ratios) in an earlier section. The resulting high impedances at various areas of the PCB can be controlled by fitting lots of decoupling capacitors, so it is only likely to be a problem for circuits operating at high frequencies with large planes and few decoupling capacitors. There is a suggestion that fitting 1 to 10nF decoupling capacitors around the edges of planes can reduce this effect.
Figure 5E shows a time domain view of how good power supply decoupling functions in an example situation. The first nanosecond or so of transient current can only be provided by local 0V/power plane capacitance, with from 1 to 3ns being provided by SMD ceramic capacitors up to 10nF located nearby.
Larger (or further away) capacitors are only able to contribute to the current demand after at least 3ns. "Bulk" capacitors (e.g. tantalums) only provide significant current after 20ns or so, even if nearby (non-ceramic dielectrics and electrolytics are slow to respond to transient current demand due to dielectric absorption effects, also known as dielectric memory or dielectric relaxation).
A PCB process is available that uses a special dielectric between adjacent 0V and power planes to increase their capacitance and eliminate the need for most of the smaller values of decoupling capacitors. Three-terminal or “feedthrough” SMD decoupling capacitors have much higher SRFs than regular two-terminal capacitors, but are more expensive. There are also laminar capacitor components (such as the Micro/Q range) made to fit under leaded ICs, which are also expensive and perhaps best used in attempts to improve existing PCBs without relaying them.
5.4.3 Decoupling without power planes
One way to achieve possibly adequate decoupling without a power plane is to connect one end of an IC's decoupling capacitor to its power pin with very short fat track, then connect that end of the capacitor to the power distribution via a thin track (to create some inductance) or ferrite bead, rated for the IC’s current. Three-terminal or high-specification capacitors may be used to advantage so that a high SRF is achieved with a single decoupler. This technique still requires a 0V plane. Where a large number of ferrite beads or expensive capacitors are required, multi-layer boards may prove to be more cost-effective and require less area.
5.5 Transmission Lines
Transmission lines maintain a chosen characteristic impedance, Z0, from a signal’s source to its load, and (as discussed in Part 2 of this series) unlike all other interconnections do not resonate however long they are. Transmission lines can easily be made on PCBs by controlling materials and dimensions and providing accurate termination resistances at source and/or load. They may also be extended off the PCB (if necessary) with appropriate controlled-impedance cables and connectors.
Comparing the length of a PCB track conductor with the wavelength of the highest frequencies of concern in the relevant medium (e.g. FR4), or with the rise- and fall-times of a signal, gives us what is called the ‘electrical length’ of the track. Electrical length may be expressed as a fraction of a wavelength or as a fraction of the rise- or fall-time. When a conductor is ‘electrically long’, transmission lines need to be used to maintain the frequency response (sometimes called ‘flatness’) or to prevent excessive distortion of the waveshape. For high-speed signals on PCBs, transmission line techniques are required for all electrically long tracks both for signal integrity and EMC.
The crude rule of thumb are that a conductor is electrically long when it exceeds one-seventh of the shortest wavelength of concern, or when the time that the leading edge of a signal takes to travel from the source to the furthest receiver exceeds half of its rise or fall times. Consider Fast TTL, which is specified as having 2ns risetimes. The dielectric constant of FR4 at high frequencies is around 4.0, which gives a signal velocity of 50% of c, or 1.5 x 108 m/s, equivalent to a track propagation time of 6.7ps/mm. In 2ns a signal in an FR4 PCB would have travelled about 300mm, so it appears that Fast TTL signals need only use transmission lines for tracks of 150mm or longer. Unfortunately, this answer is wrong. The ‘half risetime’ rule is very crude and can lead to problems if its shortcomings are not understood.
Databook specifications for output rise/fall times are maximum values, and devices almost always switch a lot faster (assume at least four times faster in the absence of actual data). It is best to measure a number of samples from different batches, and obtain an agreement from the device manufacturer that he will warn well in advance of mask-shrinks. Also, the inevitable capacitive loading from connected devices reduces the propagation velocity from what would be achieved on the bare board. So transmission lines should be used for much shorter lengths of track than suggested by the above rule, merely to achieve adequate digital signal integrity. Taking these two issues into account, we may find that specified 2ns rise/falltime signals should use transmission lines for tracks that are longer than 30mm (and possibly even less).
Transmission lines are often used for clock distribution and high-speed busses; for slower signals that have to travel further, such as SCSI and USB; and also for even slower communications such as 10base-T Ethernet and RS485, which have to travel very long distances.
Most transmission lines are used to preserve the waveshape of high-speed signals, and to reduce their emissions, but transmission-line techniques work in just the same way to reduce the amount of external fields picked-up by a track, so are valuable for EMC immunity reasons too. It may help to use transmission lines for low-bandwidth signals (e.g. analogue instrumentation) to prevent their contamination by high-frequency fields in their environment (which could be inside a product), since analogue devices are particularly prone to demodulating RF at hundreds of MHz (refer to Part 1). When designing a transmission line for immunity purposes, the ‘shortest wavelength of concern’ or the ‘highest frequency of concern’ is the important parameter.
IEC 1188-1-2 : 1998 [2], gives a wealth of details on constructing a wide variety of transmission lines with PCB tracks, plus how to specify their manufacture and check quality at goods-in. [1], [3], [4], and [5] are also very helpful with this large and detailed topic, so only the two most common types are described below.
The first example is a surface microstrip (see figure 5F), and its Z0 is given in ohms by: 
where er is the dielectric constant of the substrate (typically 4.4 for FR4 at 100MHz), B is the track width, C is the thickness of the copper material used, and H is the substrate thickness.
Its propagation velocity in ns/metre is:  .
The second example is the symmetrical stripline (figure 5G), which uses two reference planes:  .
The propagation velocity for a symmetrical stripline in ns/metre is:  .
Striplines are slightly slower than microstrip, but have zero forward crosstalk and much less off-board leakage, so are best for EMC.
[1] gives correction factors for the above formulae to compensate for capacitive loading (typically a few pF per gate):  where Cd is the sum of all capacitive loads, Z0 is the original characteristic impedance (unloaded) of the line, and C0 is the characteristic capacitance of the (unloaded) line obtained from the basic formulae given in [2].
Velocity is slowed according to the formula:  from [1], where V0 is the original (unloaded) velocity. A constant “gates per unit length” is preferred for the layout of an array of load devices, rather than bunching them together, although it may be possible to adjust the line dimensions for different portions of the track so that the same Z0 is maintained all along its length, even where load devices are bunched together.
The highest-speed (or most critical) signals should run adjacent to a 0V plane, preferably one paired with a power plane for decoupling. Less critical signals may be able to be routed against a power plane where the power plane has been adequately decoupled and is not too noisy (i.e. has been properly decoupled, see earlier). Any such power plane must be the one associated with the signal’s ICs. Striplines routed between two 0V planes (one or both of which is paired with a power plane for decoupling) give the best signal integrity and EMC.
Transmission lines must not have any breaks, gaps, or splits in any of the planes they are routed over, as these cause sudden changes in Z0. They should also stay as far away as possible from any breaks, gaps, splits, or plane edges, by at least ten times their track’s width. Low crosstalk requires spacing adjacent transmission lines by at least three times their track widths. A very critical or aggressive signal (e.g. a radio antenna connection) may benefit from using a symmetrical stripline with a row of closely spaced vias between its two 0V planes all along each side, ‘walling it off’ from other tracks and creating a coaxial type of structure in the PCB. This requires a different Z0 formula from those above.
The two transmission line types above require two or more PCB layers, so can be costly to achieve in high-volume low-cost products (although in volume a 4-layer PCB should cost no more than 20% more than a 2-layer). Balanced and co-planar line types can be constructed on a single PCB layer, so may be a solution where high-speed signals must use lowest-cost PCBs. Single-layer transmission lines will take between two and three times the area as microstrip or stripline, so be prepared for their real estate demands. Also beware of saving so much cost on the PCB that the cost of the enclosure shielding and filtering has to be increased. It is a general rule that solving an EMC problem at enclosure level costs between 10 and 100 times more than it would have if it was solved at PCB level. So when trying to pare costs to the bone by reducing the number of PCB layers, allow the time and cost for a couple of additional PCB iterations to get the EMC and signal integrity within specification and within budget, and also allow for additional PCB area.
5.5.1 Changing layers
High-speed or other critical transmission lines should not change layers. This means routing clock distribution first, moving components around to achieve the smallest area of highest-speed circuitry and tracks. High-speed busses, fast data communications, and the like are routed next, still sticking to one layer, and then everything else (less critical for signal integrity or EMC) is routed around them, changing layers as necessary. Where there is no reasonable alternative to changing the layers of a critical transmission line, a decoupling capacitor (with a suitable frequency response) should be fitted, with its vias linking all the relevant power and 0V planes, near to the point where the signal changes layers.
Keeping to the same layer is easy when using surface-mounted devices with microstrip transmission lines on the same side of the PCB. Stripline is less leaky than microstrip – but this would mean changing layers, which is generally a bad thing. (Microwave circuit designers often employ microstrip with surface-mount devices with leads that are exactly the same width as the PCB transmission line impedance (usually 50W), but they also generally fit each gain stage inside its own milled pocket in an aluminium housing. Such techniques are not generally suitable for computer and DSP boards.) Changing layers is usually necessary, if not to use striplines for their beneficial effects, then because of track densities, so how can we mitigate its effects?
We already have at least one decoupling capacitor associated with each IC (see 5.4 above) so we can change layers near to an IC, but we must consider the electrical lengths of the portions of the signal path that do not share the stripline layer. A crude rule of thumb is that these portions should not have an electrical length longer than one-eighth of the rise time (approximately one-thirtieth of the shortest wavelength of concern). Where very large changes in Z0 can occur (e.g. when using a ZIF or other IC socket) it would be better to aim for less than one-tenth of the rise time. Use these rules to determine the maximum length, and keep well within this length wherever possible.
So for signals specified as having 2ns rise time signals we should probably change layers no further than 10mm from the centre of the IC’s body or the centre of the line termination resistor. This includes a ‘safety factor’ of 4 to allow for the actual edge rate of the signal being faster than the data sheet maximum. At least one decoupling capacitor, which connects all the relevant powers and grounds together (respectively) should also be within a similar distance from any transmission line that changes layers. Such short lengths are often difficult to achieve with larger ICs, and this reveals some of the compromises inherent in modern high-speed PCB layout. This also reveals at least one reason why physically smaller ICs are preferred, and why bonding techniques such as BGA and flip-chip (which reduce the distance from the PCB track to the silicon itself) are continually being developed and improved upon.
5.5.2 Simulation and prototype testing
Because of the variations in the types of ICs, and the applications they find themselves in, some engineers will find these rules of thumb not tough enough, and some will wonder whether they are over-engineered, but that is the function of a rule of thumb, after all.
Computer-based circuit simulation techniques that calculate EMC and / or signal integrity based on parameters extracted from an actual PCB layout are becoming more capable, and their use is recommended instead of the crude rules-of-thumb expressed here. However, remember that device switching speed are almost always considerably faster than their data sheet specifications, so a simulation that uses data sheet figures will give a false sense of confidence.
Tests with a high-speed oscilloscope and probing system should be carried out on the first PCB prototypes to see whether the waveshape is good enough. A waveshape that does not distort as it travels around the PCB is the goal, and merely following these rules of thumb is unlikely to achieve such perfection, although the result may be good enough. Close-field probing with a single-turn loop, using a high-speed ‘scope and/or a spectrum analyser, is another good way to detect signal integrity or EMC problems at prototype board level. The techniques involved in prototype testing are not discussed further here.
Even when using sophisticated modelling or simulation techniques, always perform signal integrity and EMC checks on early prototypes.
5.5.3 Manufacturing issues with transmission lines
Normal FR4 PCB material has a nominal relative dielectric constant (er) of approximately 4.7 at 1MHz falling roughly in a linear fashion with increasing frequency to 4.2 at 1GHz. Actual values of er, can vary by ±25%. Controlled er grades of FR4 are available at little or no extra cost, but PCB manufacturers may not use these grades unless specifically requested.
PCB manufacturers work with standard thickness laminations (“prepregs”), and their thicknesses should be discovered (along with their manufacturing tolerances) before design starts. The track widths can then be chosen to achieve the required Z0 for the available range of dielectric thicknesses. Track widths after PCB processing are usually about one thousandth of an inch less than those used on the photoplots. Ask what thickness to add to the drawn tracks to achieve the required finished track widths.
For signal frequencies greater than 1GHz it may be necessary to use other dielectric materials than FR4, such as those used for microwave applications (e.g. Duroid from Rogers Corporation Inc., or a number of more modern dielectrics).
5.5.4 Terminating transmission lines
“Classical” RF transmission lines are terminated both at signal source and load by impedances equal to their Z0 (allowing for the internal impedances of source and load devices). Although an ideal and sometimes necessary technique, it halves the received voltage – so most ordinary analogue and digital circuits use low-Z sources and high-Z loads with the line only terminated at one end, to preserve signal levels.
RF engineers often use reactive components or even lengths of track as line terminations, but the terminations for wideband analogue and conventional digital signals require individual resistors, preferably SMD types for their excellent high-frequency performance. To get the best from SMD resistors they must be connected to the reference planes using low inductance techniques as shown by figure 5C.
Figure 5H shows the common termination techniques. Classical RF termination is still often used for high-speed signals such as fast backplane systems.
Where signals are restricted to a single PCB, series (source) termination may be used at the driver end of a transmission line, with the resistor chosen so that in series with the impedance of the output driver it matches the line’s Z0. This method has the advantage of consuming little power, and is most suitable for lines with a single load device at their far end. Where other loads exist along the length of the line they experience "reflected wave switching" and their response may need to be slowed to prevent false clocking.
Parallel (shunt, or load) termination at the very far end of a line is used where there are a number of devices spread along the length of the line and they need to respond most quickly, and achieves “incident wave switching”. Figure 5H shows the termination resistor connected to the 0V plane, but some logic families use other reference voltages (e.g. the positive plane for ECL). Parallel termination dissipates a lot of power, and may also load some IC outputs too heavily.
Alternative types of parallel termination include "Thévenin" and RC. Thévenin uses resistor values designed so that their parallel resistance is Z0 and they would provide a DC voltage at their junction equal to the average line voltage, to minimise power dissipation. Thévenin termination needs a properly decoupled power plane at all frequencies of concern so needs decoupling capacitors nearby. RC termination uses capacitor values between 10 and 620pF (typically) and only terminates the line for high frequencies. Because of the problems of capacitors (discussed earlier) it may be more difficult for an RC termination to equal the highest frequency performance of a parallel resistor or Thévenin termination.
"Active termination" uses a voltage regulator to drive an additional power plane at the nominal average value of the digital signals. A parallel line termination connects to this plane, which must be properly decoupled for the frequencies of concern. Electrically equivalent to the Thévenin method, this can save power by running the voltage regulator (which needs to be able to source as well as sink current) in Class AB.
Where a line is driven bi-directionally the compromise position for terminating resistors (series or parallel) is in the centre of the line, so such lines should always be kept very short and may not be able to run as fast as the device speeds may suggest. Series terminations at all possible drivers may be used instead of series termination at the centre of the line, but this may not give good signal integrity unless all the lines concerned are very short. Parallel termination at both ends of the line can give very good performance and allows the highest data rates, but drivers must capable of driving the resulting lower impedances, and power dissipation will also increase. Parallel (or Thévenin or active) termination at both ends is used for serial or parallel data cables such as SCSI and Ethernet.
When “star” connecting a number of individual series-terminated transmission lines, either use one termination resistor chosen so that the total source resistance equals the parallel combination of all the starred lines, or else use one resistor to match each line. The latter technique should be better. The star configuration may also be used to drive multiple parallel-terminated lines. In either case, the signal source must be capable of driving the parallel combination of all the lines' Z0s.
It is generally better to choose higher values of Z0 to reduce signal currents and reduce radiation from the tracks. Many ordinary CMOS or TTL ICs were never designed for driving transmission lines, and have neither the drive capability or an output impedance that is equal for both sourcing and sinking. Such devices may be able to use series, Thevenin, RC, or active terminations on high-impedance lines, but the best method to use, and the line impedance, may be difficult to predict for a given logic family.
However, an increasing number of devices are becoming available to drive transmission lines, and the increasing range of LVDS and similar devices is making clock and bus driving much easier and easing EMC problems. Backplane bus driver ICs are available with 25W output impedances, suitable for “star” driving four individual 100W, or six 150W lines. Some devices now have on-chip DC/DC converters which cause their unloaded outputs to achieve double the correct logic levels, so that when operated into a classically terminated line the received logic levels are correct.
5.5.5 Layer "stack up"
The above section on decoupling shows it is good EMC practice to provide 0V and power planes on adjacent layers and to maximise their capacitance by using a thin dielectric (say 0.15mm) between them. The above section on transmission lines shows that proximity to a reference plane is important for high-speed tracks. We can put this all together to decide how to stack up our PCB layers.
Four-layer PCBs often have their layers stacked as follows:
1) Microstrip transmission lines and other critical signals
2) 0V plane
3) +5V plane
4) Non-critical signals
Where more signal layers are required, a 0V and power plane "core" should be retained. Additional layers of high-speed signals may need additional 0V planes to be added, but high-speed clocks and data busses and similarly aggressive or very critical tracks should not swap layers.
Here is one of a number of possible stack-ups for an 8-layer computer motherboard:
1) 0Vplane
2) Most critical “offset striplines” and other signals, routed at 90o to layer 3) to reduce crosstalk
3) Most critical “offset striplines” and other signals, routed at 90o to layer 2) to reduce crosstalk
4) 0V plane
5) +5V plane
6) Non-critical signals routed at right angles to layer 7) to reduce crosstalk
7) Less critical “offset striplines” and other signals, routed at 90o to layer 6) to reduce crosstalk
8) 0V plane
5.5.6 Joints, stubs, and buffers
The above has treated transmission lines as if they were all point-to-point connections, so we need to address bussed systems such as RAM arrays, and situations where several cards interconnect at high speeds, such as backplane systems.
A length of track that springs off from a joint with the main track is called a ‘stub’. For memory arrays, the usual PCB layout technique is to route busses horizontally on one layer, ‘via-d’ through to another layer with vertically routed stubs to connect to the array devices. To preserve the transmission line the electrical length of the stubs must be kept to under one-eighth of the rise time (and preferably much less). Don’t forget that the important parameter is the real switching rate of the signals, not the data sheet specification of the drivers. If in doubt, assume the drivers switch four time faster than their data sheet maxima.
The stub length used for the calculation should include the distance from the end of the track (the IC’s soldered pin) to the centre of the IC itself. Where the permissible stub length is too short for traditional ‘horizontal and vertical’ array routing, daisy chain tracking should be used instead. Daisy chain tracking is generally better for high-speed signals in any case, especially when the tracks remain all on one layer. Daisy chain tracking means that the bussed tracks go from the source directly to each load in turn. Abrupt changes in track direction should be avoided, with gentle curves or large chamfers used instead. In an incident wave system, the daisy-chained tracks would end in the parallel, Thevenin, RC, or active termination resistors.
When electrically long stubs can’t be avoided, buffers should be fitted close to the main track to minimise the stub lengths. This is often used in backplane systems, where a number of plug-in cards must all run from the same clock lines and data busses, as shown in Figure 5J. The clock buffers must all be fitted very close to the backplane board connectors, and as signal speeds and data rates increase it is more common to find that matched-impedance backplane connectors are needed. Where a plug-in card only has one or two ICs that need to connect to the backplane clock and data lines, by placing them close the backplane connector it may be possible to do without the buffers.
Buffering is also a good technique for reducing the loading on a transmission line. For example, where there are ten plug-in cards each with ten ICs, all receiving one signal, their combined load capacitance can be around 400pF. The signal and return currents for this high value of capacitance have a long way to flow, increasing the likelihood that they will create EMC problems. Buffering the signal at each card means that the main line is only loaded by around 40pF, while the signal and return currents for the ten devices on each card now flow only in that card, improving signal integrity and reducing EMC problems.
Carrying high-speed signals through connectors and backplanes, it is important (vital for transmission lines) to maintain the same physical structure. For example, striplines in plug-in boards should be continued as striplines in the backplane, (although it is possible with some degradation in signal integrity to swap from one type of transmission line to another as long as the track dimensions maintain the same Z0). Where transmission lines entering a backplane connector are routed against a power plane, that power plane should be continued through the connector into a power plane in the backplane and then to the associated power planes in the other cards using that signal. The interconnections between the power planes in the boards and the backplane should be designed in the same way as for the 0V return planes. Some boards may find that their optimum backplane connector pinning needs to be: 0V, signal 1, +5V, signal 2, 0V, signal 3, +5V, signal 4, 0V, ….etc.
5.5.7 Segregation in backplane systems
Section 5.1 above said high-speed devices should be kept in the middle of their segregated area, well away from any PCB or reference plane edges, or connectors. The backplane system described above and in Figure 5J places the fastest ICs close to the backplane connector but does not compromise the earlier rules if the backplane is designed to be an extension of the plug-in boards at high frequencies.
This requires RF bonding the reference planes in the backplane to the corresponding reference planes in the plug-in boards, so that at the highest frequency of concern there appears to be no impedance discontinuity between them. Using shielded connectors helps - their shields should bond their mating halves to each other in 360o (refer to Part 2 of this series), and also bond all along their length to the 0V reference plane on both sides. Whether shielded connectors are used or not, there should be one signal return pin for every one or two (at most) signal or power pins in the connector, and these return pins should be spaced fairly regularly along the entire length of the connector. Most designers would place the return pins according to a regular scheme, but there is some evidence that a randomised allocation can have benefits. Impedance-matched connectors will almost always have a return pin alongside every signal pin, in any case.
It is important to make sure that all the high-speed devices associated with the backplane connector are closer to the middle of the connector, and do not go near to the outer edges of the boards, near the ends of the connector. It is best if the backplane connector extends to occupy the entire length of the card edge, but if it can’t it should still extend well to both sides of the area of the high-speed devices associated with the backplane connector.
5.6 Useful references
[1] M. Montrose, EMC and the Printed Circuit Board, design, theory, and layout made simple,
IEEE Press, 1999, ISBN 0-7803-4703-X
[2] IEC 61188-1-2 : 1998 Printed Boards and Printed Board Assemblies – Design and use.
Part 1-2: Generic Requirements – Controlled Impedance, www.iec.ch.
[3] IPC-2141, Controlled Impedance Circuit Boards and High Speed Logic Design,
Institute for Interconnecting and Packaging Electronics Circuits, April 1996, www.ipc.org.
[4] T Williams, EMC for Product Designers 3rd Edition, Newnes, 1992, ISBN 0-7506-4930-5, www.newnespress.com.
[5] H W Johnson and M Graham, High Speed Digital Design, a Handbook of Black Magic,
Prentice Hall, 1993, ISBN 0-13-39-5724-1. |
