The project EMC lifecycle
The EMC issues in a new project lifecycle are summarised below:
· Establishment of the target electromagnetic specifications for the new product, including:
¡ The electromagnetic environment it must withstand (including continuous, high-probability, and low-probability disturbance events) and the degradation in performance to be allowed during disturbance events;
¡ Its possible proximity to sensitive apparatus and allowable consequences, hence the emissions specifications;
¡ Whether there are any safety issues requiring additional electromagnetic performance specifications. Safety compliance is covered by safety directives, not by EMC Directive;
¡ All the EMC standards to be met, regulatory compliance documentation to be created, and how much “due diligence” to apply in each case (consider all markets, any customers’ in-house specifications, etc.).
· System design:
¡ Employ system-level best-practices (“bottom-up”);
¡ flow the “top-level” EMC specifications down into the various system blocks (“top-down”).
· System block (electronic) designs:
¡ Employ electrical/electronic hardware design best-practices (“bottom-up”) (covered by these six articles);
¡ Simulate EMC of designs prior to creating hardware, perform simple EMC tests on early prototypes, more standardised EMC tests on first production issue.
· Employ best-practice EMC techniques in software design.
· Achieve regulatory compliance for all target markets.
· Employ EMC techniques in QA to control:
¡ All changes in assembly, including wiring routes and component substitutions;
¡ All electrical/electronic/mechanical design modifications and software bug-fixes;
¡ All variants.
· Sell only into the markets originally designed for;
¡ To add new markets go through the initial electromagnetic specification stage again.
· Investigate all complaints of interference problems
¡ Feed any resulting improvements to design back into existing designs and new products (a corrective action loop).
This may look quite daunting, but it is only what successful professional marketeers and engineers already know to do, so as not to expose their company to excessive commercial and/or legal risks.
As electronic technology becomes more advanced, more advanced management and design techniques (such as EMC) are required. There is no escaping the ratcheting effects of new electronic technologies if a company wants to remain profitable and competitive. But new electronics technologies are creating the worlds largest market, expected to exceed US$1 trillion annually in value (that’s $1 million million) within a couple of years and continue to increase at 15% or so per annum after that. Rewards are there for those that can take the pace.
The following outlines a number of the most important best-EMC-practices. They deal with “what” and “how” issues, rather than with why they are needed or why they work. A good understanding of the basics of EMC is a great benefit in helping to prevent under or over-engineering, but goes beyond the scope of these articles.
1.Circuit design and choice of components for EMC
Correct choice of active and passive components, and good circuit design techniques used from the beginning of a new design and development project, will help achieve EMC compliance in the most cost-effective way, reducing the cost, size, and weight of the eventual filtering and shielding required.
These techniques also improve digital signal integrity and analogue signal-to-noise, and can save at least one iteration of hardware and software. This will help new products achieve their functional specifications, and get to market, earlier. These EMC techniques should be seen as a part of a company’s competitive edge, for maximum commercial benefit.
1.1Digital components and circuit design for EMC
1.1.1 Choosing components
Most digital IC manufacturers have at least one glue-logic range with low emissions, and a few versions of I/O chips with improved immunity to ESD. Some offer VLSI in “EMC friendly” versions (some “EMC” microprocessors have 40 dB lower emissions than regular versions).
Most digital circuits are clocked with squarewaves, which have a very high harmonic content, as shown by Figure 1.
The faster the clock rate, and the sharper the edges, the higher the frequency and emissions levels of the harmonics.
So always choose the slowest clock rate, and the slowest edge rate that will still allow the product to achieve its specification. Never use AC when HC will do. Never use HC when CMOS 4000 will do.
Choose integrated circuits with advanced signal integrity and EMC features, such as:
· Adjacent, multiple, or centre-pinned power and ground.
Adjacent ground and power pins, multiple ground and power pins, and centre-pinned power and ground all help maximise the mutual inductance between power and ground current paths, and minimise their self-inductance, reducing the current loop area of the power supply currents and helping decoupling to work more effectively. This reduces problems for EMC and ground-bounce.
· Reduced output voltage swing and controlled slew rates.
Reduced output voltage swing and controlled slew rates both reduce the dV/dt and dI/dt of the signals and can reduce emissions by several dB. Although these techniques improve emissions, they could worsen immunity in some situations, so a compromise may be needed
· Transmission-line matching I/Os.
ICs with outputs capable of matching to transmission-lines are needed when high-speed signals have to be sent down long conductors. E.g. bus drivers are available which will drive a 25W shunt-terminated load. These will drive 1 off 25W transmission line (e.g. RAMBUS); or will drive 2 off 50W lines, 4 off 100W lines, or 6 off 150W lines (when star-connected).
· Balanced signalling.
Balanced signalling uses ± (differential) signals and does not use 0V as its signal return. Such ICs are very helpful when driving high-speed signals (e.g. clocks > 66MHz) because they help to preserve signal integrity and also can considerably improve common-mode emissions and immunity.
· Low ground bounce.
ICs with low ground-bounce will generally be better for EMC too.
· Low levels of emissions.
Most digital IC manufacturers offer glue-logic ranges with low emissions. For instance ACQ and ACTQ have lower emissions than AC and ACT. Some offer VLSI in “EMC friendly” versions, for example Philips have at least two 80C51 microprocessor models which are up to 40dB quieter than their other 80C51 products.
· Non-saturating logic preferred.
Non-saturating logic is preferred, because its rise and fall times tend to be smoother (slew-rate controlled) and so contain lower levels of high-order harmonics than saturating logic such as TTL.
· High levels of immunity to ESD and other disturbing phenomena.
Serial communications devices (e.g. RS232, RS 485) are available with high levels of immunity to ESD and other transients on their pins. If their immunity performance isn’t specified to at least the same standards and levels that you need for your product, additional suppression components will be needed.
· Low input capacitance.
Low input capacitance devices help to reduce the current peaks which occur whenever a logic state changes, and hence reduce the magnetic field emissions and ground return currents (both prime causes of digital emissions).
· Low levels of power supply transient currents.
Totem-pole output stages in digital ICs go through a brief period when both devices are on, whenever they switch from one state to the other. During this brief period the supply rail is shorted to 0V, and the power supply current transient can exceed the signal’s output current. Both the transient current (sometimes called the ‘shoot-through’ current) and the voltage noise it causes on the power rails are prime causes of emissions. Relevant parameters may include the transient current’s peak value, its dI/dt (or frequency spectrum) and its total charge, any/all of which can be important for the correct design of the power supply’s decoupling. ICs with specified low levels of power supply transients should be chosen where possible.
· Output drive capability no larger than need for the application.
The output drive current of an IC (especially a bus driver) should be no larger than is needed. Drivers rated for a higher current have larger output transistors, which can mean considerably larger power supply transients. Their increased drive capability can also mean that the traces they drive can experience faster rise and falltimes than are needed, leading to increased overshoot and ringing problems for signal integrity as well as higher levels of RF emissions.
All of the above should have guaranteed minimum or maximum (as appropriate) specifications (or at least typical specifications) in their data sheets.
Second-sourced parts (with the same type number and specifications but from different manufacturers) can have significantly different EMC performance – something it is important to control in production to ensure continuing compliance in serial manufacture. If products haven’t been EMC tested with the alternative ICs fitted, it will be best to stick with a single source.
Suppliers of high-technology ICs may provide detailed EMC design instructions, as Intel does for its Pentium MMO chips. Get them, and follow them closely. Detailed EMC design advice shows that the manufacturer cares about the real needs of his customers, and may tip the balance when choosing devices.
Some FPGAs (and maybe other ICs) now have the ability to program the slew rate, output drive capability and/or output impedance of their drive signals. Their drive characteristics can be adjusted to give better signal integrity and/or EMC performance and this should help save time in development by reducing the need to replace ICs, change the values of components on the PCB, or modify the PCB layout.
Where ICs’ EMC performances are unknown, correct selection at an early design stage can be made by EMC testing a variety of contenders in a simple standard functional circuit that at least runs their clocks, preferably performs operations on high-rate data too.
Testing for emissions can easily be done in a few minutes on a standard test bench with a close-field magnetic loop probe connected to a spectrum analyser (or a wideband oscilloscope). Some devices will be obviously much quieter than others. Testing for immunity can use the same probe connected to the output of a signal generator (continuous RF or transient) – but if it is a proprietary probe (and not just a shorted turn of wire) first check that its power handling is adequate.
Close-field probes need to be held almost touching the devices or PCBs being probed. To locate the “hottest spots” and maximise probe orientation they should first be scanned in a horizontal and vertical matrix over the whole area (holding the probe in different orientations at 90o to each other for each direction), then concentrating on the areas with the strongest signals.
1.1.2 Batch and mask-shrink problems
Some batches of ICs with the same type numbers and manufacturers can have different EMC performance.
Semiconductor manufacturers are always trying to improve the yields they get from a silicon wafer, and one way of doing this is to mask-shrink the ICs so they are smaller. Mask-shrunk ICs can have significantly different EMC performance, because smaller devices means:
· less energy is required (in terms of voltage, current, power or charge) to control the internal transistors, which can mean lowered levels of immunity
· thinner oxide layers, which can mean less immunity to damage from ESD, surge, or overvoltage
· lower thermal capacity of internal transistors can mean higher susceptibility to electrical overstress
· faster operation of transistors, which can mean higher levels of emissions and higher frequencies of emissions.
Large users can usually arrange to get advance warnings of mask-shrinks so they can buy enough of the ‘old’ ICs to keep them in production while they find out how to deal with the changed EMC from the new mask-shrunk IC.
It is possible to perform simple goods-in checks of IC EMC performance to see whether a new batch has different EMC performance, for whatever reason. This helps discover problems early on, and so save money.
Alternatively, sample-based EMC testing in serial manufacture is required to avoid shipping non-compliant or unreliable products, but it is much more costly to detect components with changed EMC performance this way than it is at goods-in. |
