1.1.3 IC sockets are bad
IC sockets are very bad for EMC, and directly soldered surface-mount chips (or chip and wire, or similar direct chip termination techniques) are preferred. Smaller ICs with smaller bondwires and leadframes are better, with BGA and similar styles of chip packaging being the best possible to date.
Often the emissions and susceptibility of non-volatile memory mounted on sockets (or, worse still, sockets containing battery backup) ruin the EMC of an otherwise good design. Field-programmable low-profile SMD non-volatile memory ICs soldered direct to the PCB are preferred.
Motherboards with ZIF sockets and spring-mounted heatsinks for their processors (to allow easy upgrading) are going to require additional costs on filtering and shielding, even so it will help to choose surface-mounted ZIF sockets with the shortest lengths of internal metalwork for their contacts.
1.1.4 Circuit techniques
· Level detection (rather than edge-detection) preferred for control inputs and keypresses.
Use level detection ICs for all control inputs and keypresses. Edge detecting ICs are very sensitive to high-frequency interference such as ESD. (If control signals need to use such very high rates that they need to use edge-detecting devices, they should be treated for EMC as for any other high-speed communication link.)
· Use digital edge-rates that are as slow and smooth as possible should be used wherever possible, especially for long PCB traces and wired interconnections (without compromising skew limits).
Where skew is not a problem very slow edges should be used (could be ‘squared-up’ with Schmitt gates where locally necessary).
· On prototype PCBs allow for control of logic edge speed or bandwidths (e.g. with soft ferrite beads, series resistors, RC or Tee filters at driven ends).
Many IC data books don’t specify their output rise or fall times at all (or only specify the maximum times, leaving typical rates unspecified). Because it is often necessary to control unwanted harmonics, it is advisable to make provision for control of logic edge speed or bandwidths, (on prototype PCBs at least).
Series resistors or ferrite beads are usually the best way to control edge rates and unwanted harmonics, although R-C-R tee filters can also be used and may be able to give better control of harmonics where transmission lines are used. (simple capacitors to ground can increase output transient currents and increase emissions.)
· Keep load capacitance low.
This reduces the output current transient when the logic state changes over and helps to reduce magnetic field emissions, ground bounce, and transient voltage drops in the ground plane and power supply, all important issues for EMC.
· Fit pull-ups for open-collector drivers near to their output devices, using the highest resistor values that will work.
This helps reduce the current loop area and the maximum current, and so helps to reduce magnetic field emissions. However, this could worsen immunity performance in some situations, so a compromise may be needed.
· Keep high speed devices far away from connectors and wires.
Coupling (e.g. crosstalk) can occur between the metallisation, bond wires, and lead frame inside an IC and other conductors nearby. These coupled voltages and currents can greatly increase CM emissions at high frequencies. So keep high speed devices away from all connectors, wires, cables, and other conductors. The only exception is high-speed connectors dedicated to that IC (e.g. motherboard connectors).
When a product is finally assembled, flexible wires and cables inside may lie in a variety of positions. Ensure that no wires or cables can lie near any high-speed devices. (Products without internal wires or cables are usually easier to make EMC compliant anyway.)
A heatsink is an example of a conductor, and clearly can’t be located a long way away from the IC it is to be cooling. But heatsinks can suffer from coupled signals from inside an IC just like any other conductor. The usual technique is to isolate the heatsink from the IC with a thermal conductor (the thicker the better as long as thermal dissipation targets are met), then ‘ground’ the heatsink to the local ground plane with many very short connections (the mechanical fixings can often be used).
· A good quality watchdog that ‘keeps on barking’ is required.
Interference often occurs in bursts lasting for tens or hundreds of milliseconds. A watchdog which is supposed to restart a processor will be no good if it allows the processor to be crashed or hung permanently by later parts of the same burst that first triggered the watchdog. So it is best if the watchdog is an astable (not a monostable) that will keep on timing out and resetting the microprocessor until it detects a successful reboot. (Don’t forget that the watchdog’s timeout period must be longer than the processor’s rebooting time.)
AC-coupling of the watchdog input from a programmable port on the micro helps ensure reliable watchdog operation. For more on watchdogs, see section 7.2.3 in [1].
· An accurate power monitor is needed (sometimes called a ‘brownout’ monitor).
Power supply dips, dropouts interruptions, sags, and brownouts can make the logic’s DC rail drop below the voltage required for the correct operation of logic ICs, leading to incorrect functioning and sometimes over-writing areas of memory with corrupt instructions or data. So an accurate power monitor is required to protect memory and prevent erroneous control activity. Simple resistor-capacitor ‘power-on reset’ circuits are almost certainly inadequate.
· Never use programmable watchdogs or brownout monitors.
Because programmable devices can have their programs corrupted by interference, programmable devices must not be used for watchdog or power monitor functions.
· Appropriate circuit and software techniques also required for power monitors and watchdogs so that they cope with most eventualities, depending on the criticality of the product, (not discussed further in this series of articles).
· High quality RF bypassing (decoupling) of power supplies is vital at every power or reference voltage pin of an IC (refer to Part 5 of this series).
· High quality RF reference potential and return-current planes (usually abbreviated to ‘ground planes’) are needed for all digital circuits (refer to Part 5 of this series).
· Use transmission line techniques wherever the rise/fall time of the logic signal edge is shorter than the “round trip time” of the signal in the PCB track (transmission lines are described in detail in the 5th article in this series).
Rule of thumb: round trip time equals 13ps for every millimetre of track length. For best EMC it may be necessary to use transmission line techniques for tracks which are even shorter than this rule of thumb suggests.
· Asynchronous processing is preferred.
Asynchronous (naturally clocked) techniques have much lower emissions than synchronous logic, and much lower power consumption too. ARM have been developing asynchronous processors for many years, and other manufacturers are now beginning to produce asynchronous products.
One of the limitations on designing asynchronous ICs was the lack of suitable design tools (e.g. timing analysers). But at least one asynchronous IC design tool is now commercially available.
Some digital ICs emit high level fields from their own bodies, and often benefit from being shielded by their own little metal box soldered to the PCB ground plane. Shielding at PCB level is very low-cost, but can’t always be applied to devices that run hot and need free air circulation.
Clock circuits are usually the worst offenders for emissions, and their PCB tracks will be the most critical nets on a PCB, requiring component layout to be adjusted to minimise clock track length and keep each clock track on one layer with no via holes.
When a clock must travel a long distance to a number of loads, fit a clock buffer near the loads so the long track (or wire) has smaller currents in it. Where relative skew is not a problem clock edges in the long track should be well-rounded, even sine-waves, squared up by the buffer near the loads.
1.1.5 Spread-spectrum clocking
So-called "spread-spectrum clocking" is a recent technique that reduces the measured emissions, although it doesn't actually reduce the instantaneous emitted power so could still cause the same levels of interference with some fast-responding devices. It modulates the clock frequency by 1 or 2% to spread the harmonics and give a lower peak measurement on CISPR16 or FCC emissions tests. The reduction in measured emissions relies upon the bandwidths and integration time constants of the test receivers, so is a bit of a trick, but has been accepted by the FCC and is in common use in the US and EU. The modulation rates in the audio band so as not to compromise clock squareness specifications.
Figure 2 shows an example of an emission improvement for one clock harmonic.
Debate continues about the possible effects of spread-spectrum clocking on complex digital ICs with the suppliers claiming no problems and some pundits still urging caution, but at least one major manufacturer of high-quality PC motherboards is using this technique as standard on new products.
Spread-spectrum clocking should not be used for timing-critical communications links, such as Ethernet, Fibre channel, FDDI, ATM, SONET, and ADSL.
Most of the problems with emissions from digital circuits are due to synchronous clocking. Asynchronous logic techniques (such as the AMULET microprocessors being developed by Prof. Steve Furber’s group at UMIST) will dramatically reduce the total amount of emissions and also achieve a true spread-spectrum instead of concentrating emissions at narrow clock harmonics.
1.2 Analogue components and circuit design
1.2.1 Choosing analogue components
Choosing analogue components for EMC is not as straightforward as for digital because of the greater variety of output waveshapes. But as a general rule for low emissions in high-frequency analogue circuits: slew rates, voltage swings, and output drive current capability should be selected for the minimum necessary to achieve the function (given device and circuit tolerances, temperature, etc.).
But the biggest problem for most analogue ICs in low-frequency applications is their susceptibility to demodulating radio frequency signals which are outside their linear band of operation, and there are few if any data sheet specifications which can act as a guide for this. Specifications and standards for immunity testing of ICs are being developed, and in the future it may be possible to buy ICs which have EMC specifications on their data sheets.
Different batches, second-sourced, or mask-shrunk analogue ICs can have significantly different EMC performance for both emissions and immunity. It is important to control these issues by design, testing, or purchasing to ensure continuing compliance in serial manufacture, and some suitable techniques were described earlier (section on choosing digital ICs).
Manufacturers of sensitive or high-speed analogue parts (and data converters) often publish EMC or signal-to-noise application notes for circuit design and/or PCB layout. This usually shows they have some care for the real needs of their customers, and may help tip the balance when making a purchasing decision.
1.2.2 Preventing demodulation problems
Most of the immunity problems with analogue devices are caused by RF demodulation.
Opamps are very sensitive to RF interference on all their pins, regardless of the feedback schemes employed (see Figure 3).
All semiconductors demodulate RF. Demodulation is more common problem for analogue circuits, but can produce more catastrophic effects in digital circuits (when software gets corrupted).
Even slow opamps will happily demodulate interference up to cellphone frequencies and beyond, as shown by the real product test results of Figure 4. To help prevent demodulation, analogue circuits need to remain linear and stable during interference. This is a particular problem for feedback circuits. Test the stability and linearity of the feedback circuit by removing all input and output loads and filters, then injecting very fast-edged (<1ns risetime) square waves into inputs (and possibly into outputs and power supplies, via small capacitors). The test signal amplitude is set so that the output pk-pk is about 30% maximum, to prevent clipping. The test signal’s fundamental frequency should be near the centre of the intended passband of the circuit.
The circuit’s output is observed with a 100MHz (at least) oscilloscope and probes for its slew rate, overshoot and ringing, even for audio or instrument circuits. For higher-speed analogue circuits use an appropriately faster ‘scope and take great care to use appropriate high-speed probing techniques.
Feedback circuits should be adjusted so that slew rates are maximised, overshoots are low (heights of more than 50% of the signal’s nominal height indicate instability). Any long periods of ringing (say, longer than two cycles) or bursts of oscillation also indicate instability.
Different batches of ICs can have very different stability performance, most easily simulated by cooling and heating the device under test over a wide range of temperatures (say: -30 to + 180oC) and ensuring the circuit is as fast and stable as it is possible to achieve over the whole temperature range.
Testing could use a swept frequency instead, with a spectrum analyser at the output. Take care not to overdrive the spectrum analyser’s input.
1.2.3 Other analogue circuit techniques
Achieving good stability in feedback circuits usually requires that capacitive loads be buffered with a small resistance or choke which is outside the feedback loop.
Integrator feedback circuits usually need a small resistor (often around 560W) in series with every integrator capacitor larger than about 10pF.
Never try to filter or control RF bandwidth for EMC with active circuits – only use passive (preferably RC) filters outside any feedback loops. The integrator feedback method is only effective at frequencies where the opamp has considerably more open-loop gain than the closed-loop gain required by its circuit. It cannot control frequency response at higher frequencies.
Having achieved a stable and linear circuit, all of its connections might need protecting by passive filters or other suppression methods (e.g. opto-isolators). Any digital circuits in the same product will cause noise on all internal interconnections, and all external connections will suffer from the external electromagnetic environment.
Filtering is covered in Part 3 of this series, and the filters associated with an IC should connect to its local 0V plane. Filter design can be combined with galvanic isolation (e.g. a transformer) to provide protection from DC to many GHz. Using balanced (differential) inputs and outputs can help reduce filter size while maintaining good rejection at lower frequencies.
Input or output filters are always needed where external cables are connected, but may not be necessary where opamps interconnect with other opamps by PCB traces over a dedicated 0V plane. Any wired interconnections inside unshielded enclosures might need filtering due to their antenna effect, as might wired interconnections inside shielded enclosures which also contain digital processing or switch-mode converters.
Analogue ICs need high-quality RF decoupling of all their power supplies and voltage reference pins, just as do digital ICs. RF decoupling techniques are described later in this volume.
But analogue ICs often need low-frequency power supply bypassing because the power supply noise rejection ratio (PSRR) of analogue parts are usually increasingly poor for frequencies above 1kHz. RC or LC filtering of each analogue power rail at each opamp, comparator, or data converter, may be needed. The corner frequency and slope of such power supply filters should compensate for the corner frequency and slope of device PSRR, to achieve the desired PSRR over the whole frequency range of interest.
Transmission line techniques may be essential for high-speed analogue signals (e.g. RF signals) depending on the length of their connection and the highest frequency to be communicated (see Part 5 of this series). Even for low-frequency signals, immunity will be improved by using transmission line techniques for interconnections, since correctly matched transmission lines of any length behave as very poor antennas and don’t resonate.
Not many EMC design guides mention RF design. This is because RF designers are generally very good with most continuous EMC phenomena. However, local oscillators and IF frequencies often leak too much, so may need more attention to shielding and filtering.
Avoid the use of very high-impedance inputs or outputs. they are very sensitive to electric fields. Because the wave impedance of air is 377, electric fields dominate outside of the near field of an emissions source.
Because most of the emissions from products are caused by common-mode voltages and currents, and because most environmental electromagnetic threats (simulated by immunity testing) are common-mode, using balanced send and receive techniques in analogue circuits has many advantages for EMC, as well as for reducing crosstalk. Balanced circuits drive antiphase (±) signals over two conductors, and does not use the 0V system for the return current path. Sometimes called differential signalling.
Comparators must have hysteresis (positive feedback) to prevent false output transitions due to noise and interference, also to prevent oscillation near to the trip point. Don’t use faster output-slewing comparators than are really necessary (i.e. keep their dV/dt low).
Some analogue ICs themselves are particularly susceptible to radiated fields. They may benefit from being shielded by their own little metal box soldered to the PCB ground plane (take care to provide adequate heat dissipation too).
Figure 4B shows a simple opamp circuit (inverting amplifier) with some of the techniques described above applied. Even though the circuit uses single-ended signalling (i.e. uses 0V as the signal return) and is not balanced, common mode chokes will generally improve the EMC performance when used in the input and output filters. |
