The right methods will ensure PCB and FPGA timing and connectivity are in sync

Routing interconnect delays on the FPGA significantly affect the overall circuit performance and led to the development of physical FPGA synthesis tools. Routing interconnect delays on high-density PCBs significantly affect overall board performance and can compromise FPGA performance too. As such, a new approach is needed to solve this huge FPGA-on-board problem, and to handle easily the complexities of placing large, fast-edged FPGA devices on the PCB. These complexities can be broken down into connectivity and timing closure issues, and addressed with process integration for ease-of-use.

Often FPGAs--and, increasingly, PCBs--are designed by separate teams of designers. These design teams are quite different from each other and each has its own processes and requirements. FPGAs are primarily designed and described in a hardware description language (HDL), feeding downstream logic and physical synthesis steps. In contrast, PCB designs are still largely schematically based with no equivalent synthesis steps.

With the huge FPGA devices and packages now available (for example, the 1517-ball flip-chip BGA), it is imperative that basic connectivity data, pin data and status (locked or unlocked, and so on), can be passed easily between the diverse PCB and FPGA design processes. This information needs to be passed alongside key implementation constraints including part, speed-grade, I/O slew-rate and other buffering type constraints. Also, design changes made during the FPGA design process with the appropriate design checks need to be passed from the FPGA back to the PCB designers.

PCB librarians typically create component symbols to be used within the PCB schematic. These symbols are considered static and owned by the librarian. The large number of pins offered by the FPGA coupled with its programmability creates the need for a "custom" FPGA symbol. In many cases, the PCB logic designer chooses to create a custom symbol, so the pin names reflect the user-defined FPGA signal names for easy schematic wiring. Without these custom symbols, the PCB logic designer would be faced with connecting a signal "ABC" to "Bank_2_IOPAD_54"; a painful process when parts have in excess of 1000 pins. A custom symbol permits the PCB logic designer to wire pin "ABC" to signal "ABC." The custom symbol provides for a more expedient and less error-prone process. In addition, the custom symbol should be automatically generated based on the FPGA pin assignment file.

For larger FPGA devices (for example, the Altera Stratix and APEX-II families and the Xilinx Virtex-II and Virtex-II Pro families), schematically representing the symbol for PCB design and documentation is no longer feasible or even physically possible without violating corporate drafting standards. Bear in mind that for even the largest drawing sheet available, the maximum symbol size that can be successfully supported is around 1100 symbol pins.

The PCB designer must be able to "fracture" the FPGA symbol along functional or physical lines. Custom-symbol generation should be augmented with a fracturing capability that enables the user to create a set of custom symbols for a particular FPGA implementation (FIGURE 1). The FPGA symbol set can then be spread conveniently through the PCB schematic for efficient design creation.

[FIGURE 1 OMITTED]

In addition to the custom schematic symbols required for PCB design and layout, PCB tools need accurate and comprehensive symbol-to-part packaging data, often referred to as symbol-to-pin-mapping information.