For large and complex FPGA devices, this has been a long, tedious and error-prone process, taking designers and librarians days to create and verify the symbol and pin-mapping data before confidently proceeding to PCB layout.

(There is novel software that addresses the FPGA and PCB design process synchronization, fully automates this custom symbol and part creation process. FPGA BoardLink, which integrates with Mentor Graphics' PCB and FPGA design tools, ties the custom FPGA symbol and part-creation process into the overall corporate library environment and extracts and uses corporate library part data when generating custom symbols and custom parts for each FPGA device on the PCB.)

Ideally, the PCB designer needs to extract and include PCB interconnect effects for simulation and timing analysis, and then pass these effects easily to the FPGA designer, who immediately benefits from more accurate "Offset Constraints" for the logical and physical FPGA synthesis steps. The interconnect adds delay due to time-of-flight calculations from delay-per-unit trace length plus additional delay due to loads and topology. These modified offset constraints also need to be passed from the synthesis engine to the FPGA vendor implementation tools. Historically, this has been difficult, and compounded by the lack of a common constraint manager that could be used by both PCB and FPGA designers.

In FIGURE 2, functional simulation and timing analysis show a healthy amount of "Offset In--Before'" or "Setup" timing slack. However, actual simulation of the signal and board topology shows that the effects of the PCB interconnect have significantly reduced the amount of available timing slack. This is because the receiver will only see valid transitions when the signal levels at the receiver cross the switching thresholds. The effects are driver-strength-dependent, topology-dependent and termination-dependent.

[FIGURE 2 OMITTED]

Now the functionally estimated offset constraint has been reduced to the more accurate or actual offset constraint. This new reduced value is then passed to the FPGA design tools.

For timing closure, one option is functional simulation of the FPGA-on-board using FPGA vendor-generated standard delay format (SDF) and HDL outputs. Novel symbolic timing analysis can be used with FPGA vendor-supplied modeling information to estimate and analyze the path used to get data on and off the FPGA. In such cases, board analysis is localized around the FPGA and immediate devices, and a simple critical timing-based model used for the FPGA. Calculated or estimated offsets are used to constrain the analysis-driven PCB router, which then derives the actual offset constraints" for FPGA synthesis. The FPGA is then synthesized and placed and routed using the actual offset constraints. The FPGA timing model is generated and timing analysis can be run on either the localized FPGA area of the PCB or on the complete PCB.