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| G-LINK PCB Layout |
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Introduction
To prevent any problems with signal quality or EMC with the G-LINK HDMP1024, I've made a real effort to get the design of that part right.
I had asked a few people inside and outside CERN about possible problems with the G-LINK, as there are different 'schools' of how to use the chip. I got the following responses:
- "you should cool the chip correctly" or
- "you should only connect certain Vcc pins via a 10 Ohm resistor and certainly not put a decoupling capacitor" or
- "you should isolate the Vcc pins with filters from the Vcc plane" or
- "you should have a cutout (moat) in the ground plane for the Gnd connections" or
- "you should do nothing special (even a 2-layer board without ground plane works)"
There are no application notes from Hewlett Packard about special precautions to take; only one diagram is shown in the datasheet where basically each power pin has its own decoupling capacitor. I tried to talk to an application engineer from HP, but could not reach any.
As many of the methods described above didn't appear to be sound (for signal quality reasons), and as also some of those recommendations may add cost and complexity, I had another approach for the design of the PCB.
Local Gnd plane on the top
My method of the PCB layout for the G-LINK chip is to have a separate local ground plane directly on the top layer (see fig.1,2). This ground plane is connected with about 20 vias (14 inside the plane, 6 outside) to the real ground layer. Note that this ground plane is solidly connected to the other ground plane, and is not decoupled from it in any way as one sometimes sees.
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Figure 2: PCB layout around G-LINK, top layer
Note the solid copper ground plane under the G-LINK and the vias that connect it to the internal ground plane. Also note that the decoupling capacitors are connected to both the local ground plane and with a via to the internal ground plane |
Figure 3: Silkscreen around G-LINK, top layer
Note the eight decoupling capacitors connected very close to the G-LINK |
This method of the local ground plane on the top is for free, while it has several advantages:
- the G-LINK Gnd pins are connected directly (and not through a via) to the ground plane, therefore reducing ground bounce
- there is less EMC radiation and susceptibility as the local ground plane is very close to the G-LINK package and the actual chip
- the G-LINK is well cooled as it has directly a copper plane under it and the many vias distribute the heat directly to the Gnd plane
Decoupling capacitors very close
To give a robust power supply to the G-LINK, physically very small (of the 0603 type) SMD 100 nF capacitors, which have a very low series inductance, have been used to bypass the Vcc supplies of all Vcc pins. These capacitors are put very close (less than a few millimeters) from the G-LINK ground and power pins. The capacitors are connected in between vias (to Gnd and Vcc) and the G-LINK pins (see fig.2).
Results
The functioning of the board has been tested extensively with the help of a Japanes G-LINK board and a SLITEST, but no tests have been made of noise on the Vcc lines or EMC susceptability. I expect that measurements will be very difficult and will give no results, unless also a comparison board is made in which the layout is much different. |
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