Additional requirements for the efficient
design of high-speed buses may be
dictated by the needs of a specific application.
For example, a 266 MHz, 64-bit
DDR RAM interface will be sensitive to
skew between the different byte lanes.
Large parallel buses also have the potential
to generate simultaneous switching output
(SSO) noise and voltage droop. All of these
factors translate into the need to manage the
transient current demands of a particular
application through proper design of the
power distribution system (PDS).
Resistance, Inductance, and
Capacitance Pull the Strings
In general, SI and PI issues arise when
designers pay inadequate attention to these
broad categories:
• Termination schemes
• Skin effect (frequency-dependent
attenuation)
• Dielectric losses
• Impedance discontinuities/reflections
• Data coding (DC balanced codes, run
length, channel memory)
• Equalization/pre-emphasis
• Inter-symbol interference
• Crosstalk
• Decoupling/bypassing in power
distribution
• Board stack-up
• Signal edge rates.
The common denominator in these
problems is poor management of the three
“bad boys” of electric circuits: resistance,
inductance, and capacitance (Figure 1). In
addition, you must understand and
employ the right measurement techniques
in the lab to accurately measure
and validate designs against simulations
or design specifications.
The objective is to build systems right
the first time.
Minimize SI/PI Effects
In this special series on signal integrity, we
have assembled articles that will provide you
with practical and technical resources
towards achieving that goal. From characterization
and model extraction techniques in
the lab to methods for simulating signal
degradations of synchronous parallel/asynchronous
serial systems to case studies, this
series covers many aspects of SI.
In a sidebar to this article, Xilinx
Principal Engineer Austin Lesea lists “Ten
Reasons Why Performing SI Simulations is
a Good Idea.” Although this may sound
very familiar to some of you, understanding
the benefits of performing SI analysis
throughout the design cycle can help you
achieve your performance, reliability, and
time-to-market goals.
“Interfacing SMA Connectors to
Virtex-II Pro MGTs” details Warren Miller
and Vince Gavagan’s experience designing
the interface between Virtex-II Pro™
multi-gigabit transceivers (MGTs) and Sub
Miniature version A (SMA) connectors for
the Virtex-II Pro Aurora Design Kit.
Through prototyping and time domain
reflectometry (TDR) measurements, they
illustrate how SMA connector choice influences
signal quality.
Bill Hargin believes that “For
Synchronous Signals, Timing Is
Everything.” His article outlines a method
for extracting correction values that can be
applied to the clock-to-out and flight time
numbers. The resulting timing values in
the datasheet are representative of the actual
load and topology of your design. This
technique specifically applies to sourcesynchronous
links.
Predicting the interconnect performance
of high-speed links made of complex
via, connector, and trace structures is no
easy task. However, as Ansoft’s Lawrence
Williams explains in “Designing High-
Speed Interconnects for High-Bandwidth
FPGAs,” combining electromagnetic, circuit,
and system simulations greatly helps
in the design of reliable and fast data transmission
channels.
When designing multi-gigabit asynchronous
channels, you must carefully analyze
the link’s physical and electrical properties.
In his article, “Accurate Multi-Gigabit Link
Simulation with HSPICE,” Dr. Scott
Wedge explains how the combination of an
EM solver, coupled transmission lines, Sparameter
support, and SPICE and IBIS
modeling to the HSPICE® circuit simulator
helps accurately account for high-speed
signal distortions.
With “Eyes Wide Open,” Steve Baker
shows you how to use the RocketIO Design
Kit for ICX™ to evaluate pre-layout
options (such as placement, connectors, or
stackup) as well as post-layout options (such
as detailed routing structures) to achieve
high-speed serial link performance.
As much as Xilinx recommends SI simulation
and analysis before manufacturing a
PCB, there are two very valuable lab instruments
that you can use on prototype/exploration
boards. With these instruments, you
can characterize interconnect properties and
high-speed signal behavior, explore different
topology performances, or extract simulation
models. In his article, “Backplane Characterization Techniques,” Eric Bogatin
explains the need for making measurements,
illustrating the concept of measurement and
model bandwidth. He also discusses SMA
launches, information contained in TDR
traces, and differential S-parameters.
In “A Low-Cost Solution for Debugging
MGT Designs,” Joel Tan presents a solution
comprising a bit-error rate testing
module connected to a flexible on-chip
logic analyzer core, both implemented in
FPGA fabric. Together with the
ChipScope™ Pro software suite, these two components allow you to perform diagnostic
testing, debugging, and development of
an MGT system without the use of expensive
lab equipment such as logic analyzers
and BERT testers.
And in “Tolerance Calculations in Power
Distribution Networks,” Sun Microsystems’
Istvan Novak walks you through different
scenarios of bypass capacitor configurations
to demonstrate the importance and influence
of the capacitors’ technology, value, and
number in designing a decoupling/power
distribution network.
Conclusion
We hope you will find in this series
instructive material on the sources of
SI/PI effects, along with practical information
about the resources and tools
available to you. Our experience tells us
that careful simulations, analysis, and
measurements of PI and SI effects early in
the design process guarantees first-time
success more often than not. |
