Beginning with early HDL descriptions of the FPGA, I/O Designer's automated schematic symbol generation function provides PCB designers the schematic symbols used to represent FPGAs in the PCB design. The tool then manages pin assignments on the FPGA.

John Isaac, director of market development for Mentor's systems design division, said that PCB designers often inadvertently violate the FPGA's rules, which don't always translate into the PCB layout flow. The designer must be able to optimize the FPGA while ensuring that the correct constraints are followed.

"Sometimes the data files swapped didn't contain all the constraints and rules, and you had bad translation of your FPGA schematic into your PCB schematic. The PCB designer may have used a FPGA pin to go to another chip, and violate FPGA rules," said Isaac.

"I/O Designer allows you to feed in the rules supplied by the FPGA supplier. This gives the designer the flexibilty of assigning pins, but under the guidelines provided by the FPGA vendor."

Isaac added that when properly utilized, I/O Designer can allow designers to cut the FPGNs Manhattan distance in half.