ABSTRACT
This document serves to provide goals and objectives associated with evaluation of the
robustness and process sensitivity of various laminate materials and structures in Pbfree
assembly. The overall goals are to:
1) Generate an experimental basis and understanding for proper materials and structure
testing protocols.
2) Identify and obtain currently available robust PWB materials and components.
3) Design and build appropriate test board(s) which effectively evaluate material
damage at Pb-Free temperatures.
INTRODUCTION
There is a rapidly growing concern that cards, Printed Circuit Boards (PCB’s) and
components offered for Pb-free assembly may not all in fact be completely suitable for
this, i.e. that some may be subject to latent or maybe infrequent damage unlikely to be
detected in current experimentation and process development. One example of this
might be the delayed failure of one or a few vias or pads on an entire PCB (or maybe
not even on every PCB in a batch) under specific conditions.
Our current impression is that, at best, a very limited range of tests is often employed to
ascertain that the use of specific materials and structures may be extended to Pb-free
assembly. By nature, suppliers may certainly be expected to focus their efforts on the
cards/PCBs alone, just as component suppliers are likely to most often test the
components by themselves. We therefore have particular concerns as to additional
damage and damage mechanisms introduced when one is attached to the other. This
might for example occur as a result of the loads exerted on the card/PCB by a particular
component or connector, and perhaps only be an issue for a particular combination of
component properties (rigidity, expansion and warpage vs. temperature), dimensions
and location.
A primary goal is to identify materials and structures that are sufficiently robust in no-Pb
assembly. However, a more immediate and important one is first to learn to understand
what our concerns should be, and how to test for them. Our proposed testing is
expected to offer ongoing learning in this respect.
CARD / PCB DAMAGE
As already well established, some materials and structures may be damaged in
assembly in a wide variety of ways. Several specific problems that might be expected to
exacerbate Pb-free assembly, relative to eutectic Sn/Pb assembly include (in no
particular order):
1. Moisture uptake and degradations of insulation and dielectric performance.
2. Inner-post separation (IP SEP) and Innerconnect defects (ICD’s).
3. Reduced copper (pad) adhesion.
4. Reduced solder mask adhesion and delamination.
5. Damage to the electroless and electrolytic coppers in PTH’s and vias.
6. Reduced mechanical strength and fracture resistance.
7. Reduced chemical resistance.
8. Cracking of the laminate (notably under the pads).
9. Boards are often seen to become discolored and blister in no-Pb reflow, and they
may be warped more than in Sn/Pb reflow, both temporarily and permanently.
DAMAGE OBSERVATIONS
The development of a meaningful test plan should rely on a comprehensive review of
potential damage mechanisms. Some potential problems known to be enhanced in Pbfree
assemblies, notably those associated with metallization phenomena such as 'black
pad’ are considered to fall outside the scope of the present project (addressed as part of
other consortium projects). Others may not be properly identified or assessed until after
the work has started, so the list is likely to change over time, therefore initial input will be
solicited from industry contacts.
Like many others we have already seen delamination and blistering in no-Pb reflow of
some high-Tg FR-4 boards after extended ambient storage (and no bake-out to dry).
Blistering near/between PTHs and/or vias was reported to increase with decreasing
hole pitch, not a surprising trend.
Recently, we found no-Pb BGA assembly to lead to fine cracks in the laminate under
the pads on 4-layer .092” thick high-Tg (175C) FR-4 test boards. It appears that these
cracks tend to grow substantially in cycling, but that this growth is sensitive to
component construction (warpage). This seems to be at least partly associated with the
overall resin thickness and low metal layer count. Follow-up experiments with the same
component showed no cracking of 0.062” boards in reflow, i.e. the unusually thick
laminate layers were probably a factor. However, Sn/Pb based assembly of the same
component with the same reflow profile (245C peak) did not cause cracking of the
0.092” board either, so the higher flow stress of the Tin, Silver, Copper (SAC) alloy
joints seemed to make things worse. While the 245C peak by itself did not cause
detectable damage it may have contributed as well. Certainly, raising the peak
temperature to 270C (which may occur in some assembly unless special measures are
taken) did cause the 0.062” thick boards to crack as well, even with Sn/Pb solder.
Temperatures intermediate between 245C and 270C remain to be tested.
DAMAGE & TEST DISCUSSION
Even a typical Sn/Pb reflow is likely to weaken laminate structures somewhat. The only
question is whether this is enough to be important. Similarly, we would expect no-Pb
reflows to have a measurably enhanced effect on a number of properties. Our
observation of laminate cracking under the pads of even Sn/Pb based assemblies after
a 270C peak reflow is one illustration of such weakening. This does not necessarily
mean that all weakening effects are of practical concern. We plan to take a mechanistic
approach to damage evaluation; working to identify the root causes and quantify the
potential consequences in terms of production yields, circuit integrity, and postassembly
performance, etc.
An important part of many damage concerns is the specific (thermo) mechanical load
involved. This load does not always have to be greater than in Sn/Pb assembly for it to
become an increased concern. A no-Pb reflow profile may simply weaken the structures
so much more than a Sn/Pb profile that they can no longer always sustain the load
exerted by, say, a rigidly underfilled flip chip or a through-hole component. Some loads
will, however, invariably also be greater. Area array solder joints are almost certain to
reach their flow stress, as determined by assembly mechanics and the cooling rate,
during a substantial part of cool-down from any realistic reflow. Literature data suggest
that these stresses may be almost twice as high in typical no-Pb joints as in Sn/Pb. In
addition, cooling from higher temperatures a component may tend to warp more and
thus exert a greater out-of-plane load on the board. Large resistors and capacitors, such
as 2512s, may load contact pads and associated vias even more.
Non-uniform heating is very likely to be more damaging to both laminate and metal
structures than regular mass reflow. Wave soldering induces strong transient
temperature gradients through the thickness of the board and selective soldering
involves particularly large lateral variations as well. These problems are exacerbated in
no-Pb soldering where the higher melting points and reduced wetting call for higher
temperatures and longer times, a requirement that is further enhanced by power/ground
planes shielding layers above them from the heat and thus inhibiting the penetration of
solder up the through-holes.
Importantly, conventional IST testing of bare via chains after ‘typical’ no-Pb soldering
might easily underestimate the potential for damage. A heavy (large thermal mass)
through-hole component on the top side may strongly enhance local temperature
gradients, as well as calling for higher temperatures and/or longer heating times. In
addition, a massive component such as a power transformer may not allow for very
effective relaxation after solder solidification and may exert a particularly high load on
the board at that particular location during cool-down. To make matters worse no-Pb
wave soldering is also supposed to require faster cooling to prevent fillet lifting, further
raising loads and the risk of cracking or permanent board warpage.
Another occasion for strongly non-uniform local heating is that of repair, particularly of
large area array component with a heat spreader which may require prolonged heating
to ensure good soldering while limiting the maximum component temperature. In
addition, repair of field repairs in particular may involve boards that have degraded
somewhat after the initial no-Pb assembly process.
Finally, thermal shock testing may cause significant temperature gradients in thick
boards all by itself. In this respect, such testing is completely irrelevant to any service
conditions but underfilled flip chip assemblies are often tested in thermal shock and it
has become common to require that the board (vias) not become the limiting factor.
A somewhat special challenge is the accommodation of compliant pin or press fit
connectors. Ensuring sufficient retention force and the long-term stability of a minimum
contact resistance requires a significant loading of, and potential interior damage to, the
board. In particular, the interior of the board may be damaged during insertion of the
connectors and rework. Necessary changes to both solder and metallizations are
expected to call for increased loads in no-Pb assembly, the effects of which may be
further exacerbated by any additional weakening of the laminate structures in the higher
temperature reflow.
We emphasize that mechanical damage is not confined to cracking of laminates and
metallizations. Higher mass reflow temperatures, perhaps after some aging in storage,
may reduce pad adhesion even to the extent that the more rigid no-Pb solder joints
under an imperfectly balanced large component will tend to initiate delamination from
the underlying laminate. Potentially more critical, however, because it is even more
easily overlooked is further degradation on the shelf or in service afterwards so that the
pad, rather than the solder, suddenly becomes the weakest link after some time. In
developing tests for such concerns we note that standard peel tests tend to involve
rather wide metal strips (32-125 mil, IPC-TM-650.2.4.8) and thus are not sufficiently
sensitive to address concerns related to moderate and fine pitch assemblies.
In general, damage may lead to either opens or shorts. Localized glass-resin
debonding, perhaps initiated in hole drilling etc., but enhanced under some of the no-Pb
assembly conditions discussed above, may for example affect the insulation between
closely spaced vias and associated conductors.
No-Pb assembly is also likely to lead to enhanced board/card distortion and warpage.
As they are heated higher above the laminate Tg the multilayer structures are likely to
warp more, both temporarily at the high temperature and permanently after subsequent
cool-down. Enhanced warpage at reflow may affect assembly yields, and permanent
distortion may be a problem in subsequent assembly (double sided or if the card is part
of a component) and repair. In addition, of course, distortion may also reflect a greater
load on, or already initiated damage to, metallizations. Again, the presence of both
through-hole and surface mount components may strongly enhance such problems.
Certainly, an underfilled flip chip or CSP is likely to exacerbate distortion in subsequent
mass reflows or (selective) wave soldering.
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