Finally, repeated high temperature reflows may lead to degradation in terms of a
reduced Tg, decomposition temperature or even mechanical properties.
We need to consider not only laminates but also solder masks. Solder Masks usually
have lower Tg (120-140C) and higher CTE (60-80ppm/C). Thermal degradation may
lead to reduced adhesion to the underlying laminate, reduced solvent resistance, or
reduced encapsulant or mold adhesion to the surface. Of particular practical concern is
the resistance to solder wicking along the copper features.
Many people tend to focus on popcorning / delamination as addressed for components
in IPC/JEDEC J-STD-020B. The test (moisture exposure followed by 3 reflows)
becomes increasingly severe as the peak reflow temperature increases. A 'rule of
thumb' in the industry is supposedly that each 10oC increase reduces the achievable
JEDEC level by one. Anyway, like for other adhesive interfaces, we need to recognize
that this test is empirical and does not necessarily address the actual damage
mechanisms correctly. For example, the procedure assumes that you can 'cancel' the
effect of a moisture exposure (without reflow) by simply baking out again. We know,
however, that aging and moisture exposure may leave permanent degradation of
epoxies even after bake. Aging and moisture exposure will also tend to weaken
chemical interfaces, organic bonds, and cross-linking even if not enough to allow
popcorning in subsequent reflow. Similarly, we believe that reflows may weaken the
interfaces and initiate latent damage as well.
A somewhat special concern involves bonding of adhesives during or after no-Pb
assembly. The higher reflow temperatures might simply modify or contaminate the
solder mask surface, thus affecting the adhesion of subsequently deposited die attach
adhesives or flip chip underfills. Volatiles evolved in reflow may certainly contaminate a
flip chip surface and affect subsequent underfill adhesion there. Even prebaking does
not always prevent enhanced outgassing and voiding in no-flow underfills at the higher
reflow temperatures involved.
CURRENT PCB/ASSEMBLY TESTING
Included below is a listing of several of the major, common, commercially available
testing capabilities currently employed in the analysis of PCB’s to determine both quality
of construction and in many cases reliability specific to the circuit board:
IST - Innerconnect Stress Testing, typically, a product-specific designed coupon is
heated internally by applying DC current. The current is “powered” onto a circuit net that
daisy- chains throughout the entire coupon. Switching the current on and off heats, and
subsequently cools, the coupon to predetermined setpoints typically ranging from 260
deg C to room temperature. Repetitively, this thermal cycling induces strain/stress in the
plated thru holes and surrounding via structures, which is “sensed” as a resistance
measurement. The number of cycles completed is an assessment of PTH/Via and
interconnect performance and bare board reliability.
Reference: IPC-TM-650, 2.6.26
Acceptability: Typically 500 cycles, but dependent on PWB construction.
PCT – Pressure Cooker Test or PPOT - Pressure Pot Test, is an empirical reliability
assessment to evaluate the ability of a product to withstand severe temperature and
humidity conditions. The steam autoclave is the typical instrument used to promote and
accelerate corrosion within the test samples, by soaking at 100% relative humidity, and
2 atmospheres (15 PSI) of pressure, as the temperature is controlled at 121 deg C for
168 hours. Failures are monitored typically by resistance readings taken at 48, 96 and
hours, as well as end of test.
Reference: JESD22-A102-C / EIAJ-IC-121-18
Acceptability: Passes/Fails after 168 hours. Electrical leakage, attributable to moisture
content, must be discerned from true failure mechanisms.
LLTS/AATS – Liquid to Liquid Thermal Shock/Air to Air Thermal Shock. Either
technique, differing primarily by the thermal medium within the test chamber (Air or
Liquid) is used to determine the resistance of an assembly or PCB to sudden, drastic
changes in temperature. Samples, beginning at room temperature, are exposed and
cycled from extremely hot to extremely cold temperatures and back again to ambient
within repetitive, predetermined time windows. Varieties of test conditions exist within
the reference test methods, dependent on PWB construction and end-use of the
electronic assembly. These typically range from –65 deg C to 150 deg C. Samples are
normally monitored for resistance changes, continuously during thermal excursions to
determine “cycles to failure”.
Reference: JEDEC JESD22-A106, IPC-TM-650 2.6.7
Acceptability: 100 to 500 cycles, dependent on product construction and end use.
THB – Temperature Humidity Bias (Steady State), differing only from PCT/PPOT testing
by the application of bias voltage on the PCB/Assembly and RH/Temp settings, THB
testing employs the following, typical, stress conditions: 1000 hours at 85 deg C, 85%
RH. The bias voltage applied is usually designed to simulate the conditions of the
device in its real-life end use; maximizing variations in the potential levels of the
different metallization areas on the component die as much as possible. This is another
good candidate method for accelerated corrosion resistance.
Reference: JEDEC JESD22-A101-B
Acceptability: Passes/Fails after specified test time.
HAST - Highly Accelerated Stress Testing, was developed as an alternative to
Temperature Humidity Bias (THB) testing as well as being nearly identical to
PCT/PPOT testing criteria. Where THB testing takes 1000 hours to complete, HAST
results can be attained within 200 hours. Like THB and PCT testing, HAST accelerates
corrosion, particularly that of the die metal lines and thin film resistors. HAST however,
requires sample preconditioning and is conducted typically with electrical bias 5.5V at
130 deg C and 85% RH for a specified amount of time. It is also used for the reliability
assessment of assemblies and PCB’s suspected of being prone to corrosion due to
ionic contamination.
Reference: JEDEC JESD22-A110
Acceptability: Passes/Fails after specified test time.
Hi-Pot - or Dielectric Withstanding Voltage, (500V)
Reference: IPC-TM-650, 2.5.7
Acceptability: Condition A, Passes/Fails based on visual inspection for evidence of
dielectric breakdown or whether insulating materials and/ot conductor spaces are
adequate.
T260/T288 - Time to delamination at 260 or 288 deg C. uses the TMA to measure time
to delamination. A 5-gram force is maintained while temperature is ramped up to
260/288 C and held there for 10 minutes. Failure is determined by a measured,
permanent ‘thickness increase’ caused by subsequent blistering/delamination.
Reference: IPC-TM-650 2.4.24.1
Acceptability: Current specifications indicate 5.2 minutes min for T260.
Other / Miscellaneous Testing
Solder Pot Thermal shock (288C) – 10x: defects.
Solder float peel strength: (no change after 288C/10 sec)
HAST, 100VDC, 96 hours: no change in resistance
Humidity effect on capacitance (<10% increase from 0-90%R.H.)
High temperature and humidity storage (85/85, 30V bias, 1000 hrs)
High temperature storage (150C, 1000hrs)
Low temperature storage (-65C, 1000hrs)
Solder reflow test (235C, 10s, solderability).
TESTING SPECIFICALLY FOR NO-PB
Beyond conventional Sn/Pb testing, there has not been much progress towards
development of specific Pb-Free analytical methodology. Many of the current Sn/Pb
testing techniques still apply to Pb-Free, but it is clear that more can be done to improve
specific technique and criteria for evaluation of the thermal extension added to lead-free
product. Several of the enhanced analyticals are covered below where simply an upper
temperature has been increased or extended:
T288 by TMA, IPC test method, Time to Delamination has been developed.
Solder float IPC 288C, 10 sec has been developed.
Fracture index after 10x floats: wicking length times 2 + crazing length in mils.
A typical solder dip test involves moisture preconditioning at 121C/ 100%R.H. for 1, 3
and 6 hours, followed by dipping (submerging) in molten solder at 220C, 250C, and
280C for 5, 10, and 15 sec. In each case the samples are then analyzed for failure
mode.
A typical solder float test involves preconditioning at 85/85 for long enough to get 50, 75
and 100% saturation, then floating on molten solder at 220C, 250C, and 280C while
watching the top for blisters, white spots, etc. The time to such damage is noted. This
might be taken to represent wave in some respect.
PB-FREE BOARD DAMAGE TEST PLAN
A primary concern is the effect of actually populating a board or card with no-Pb area
array and through-hole components. As discussed above this may strongly exacerbate
board/card damage in ways that depend on the specific components and locations.
Also, even if present insidious degradation mechanisms may not always be detectable
in an unpopulated board.
Components exert highly localized mechanical loads on laminate and plating, notably in
vias, as well as on solder mask and contact pads through pins, solder joints and
underfill. All of this is sensitive to layout, component mechanics, and solder properties.
In addition, of course, both mechanical and other ‘weakening’ (reduced performance)
may be sensitive to combinations of product design, aging and actual no-Pb assembly
process parameters. Notably, non-uniform or local heating in realistic (selective) wave
soldering and repair may be more damaging than current accelerated tests.
In the long term testing should address both 'general' and HDI applications, i.e. not
automatically reject structures that may be sufficient for 'general' applications if such are
relevant for those specific structures. Starting out with a moderately thick, multilayer test
vehicle as outlined below we shall, however, focus on applications typical of such
structures.
The plan currently under consideration involves test procedures as outlined below.
These tests will, however, be accompanied by mechanistic studies to ensure our
understanding of the various damage phenomena and mechanisms. The results are
expected to lead to significant revisions of our test procedures as we go.
Laminate and Solder Mask Material Pre-Screening
Supposedly, laminates have already been characterized by the PCB supplier in terms of
a so-called fracture index associated with thermal shock and only materials with a
sufficiently high index are considered applicable to no-Pb assembly. One might
therefore also presume that materials have been inspected for visual damage as
reflected in discoloration and blistering. However, we shall not count on any of this.
Eventually we propose to pre-screen all laminates and solder masks proposed by
suppliers as no-Pb compatible, to the extent these are available. This will obviously
involve collecting and reviewing available information. For a beginning, however, we
recognize that some pre-screening procedures may arise from our initial learning. We
therefore plan for the immediate design and acquisition of the first real test structure
(below) without any pre-screening before.
Pre-screening procedures would of course have to be simple. One might involve 5-10
reflows with a peak temperature of 260oC or 270oC followed by visual assessment of
damage. We also propose to check for degradations in Tg and perhaps enhanced
moisture uptake.
This step could be based significantly on production scrap structures, if available. We
do, however, need to be sensitive to whether a particular performance characteristic
may be affected by the specific processing it has undergone.
Screening would continue in parallel with further work as new materialmaterials are identified
and made available, and as new procedures are developed.
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