Test Structures
A range of test vehicles will either be acquired as is or specifically designed to identify
and address the damage mechanisms of concern. The important criterion is that the
vehicle should specifically emphasize problems potentially arising when switching to no-
Pb assembly. This means that the vehicle should involve structures and materials that
can be expected to perform satisfactorily for Sn/Pb assembly. In fact, a considerable
experience and database should preferably exist for corresponding Sn/Pb applications.
Notably, the vehicle should not offer any particular challenge to the supplier.
It would of course be preferred that some test vehicle would include realistic deviations
from perfection such as misregistration of vias, copper thickness or width variations,
etc., albeit at a level acceptable for Sn/Pb assembly. If necessary, such deviations
might be introduced deliberately to represent variations at a level anticipated across
large manufacturing lots.
The plan is to include multi layer test vehicles with 5-10 mil thick single-ply layers and
thus a relatively high resin content that we would expect to be relatively sensitive to
higher reflow temperatures. Efforts should be made to use realistic copper thickness
and distribution (both laterally and through the thickness). This is expected to affect the
build-up of localized stresses on barrels and IP connections in manufacturing, handling,
and cycling. A typical construction would utilize both 1 oz (signal) and 2 oz (P/G)
innerlayers is currently planned.
When possible test vehicles include insulation resistance test coupons, solder float
patterns, daisy-chained via arrays connected by 3 to 8 mil traces on top and bottom
surfaces for thermal cycling, and IST coupons.
There has also been interest in incorporating populated sites in an IST structure, but we
do caution that this would seriously alter the thermal response of the structure to the
current loading and thus at the very least require extensive characterization. Preliminary
work proposes to use a 256 I/O PBGA as an IST coupon attachable component.
It is proposed that different via test patterns include vias down to 6 mil diameter on
various pitches down to 0.65mm, allowing for assessment of damage both to the vias
themselves and to the often resin rich regions between closely spaced ones. It is
emphasized that some of the vias should be connected to realistic ground planes as this
offers a particular potential for damage among others in wave soldering. It may also be
relevant to include lines routed between arrays of vias on inner signal planes? This
should not be tight enough to be a challenge to the supplier, but should represent risks
of partial damage in a no-Pb reflow which may lead to faster opens or shorts in
subsequent cycling.
A range of parameter variations should be included for testing. Both DC and pulse
plated vias should be tested, as the processes offer quite different copper grain
structures. Sn/Cu is proposed as a no-Pb alternative to HASL and should be
considered. In addition, lamination process parameters should be deliberately varied
across a realistic range and the consequences tested for.
A number of known defects may also be introduced by deliberately modifying/omitting
plating, desmear, etch, and copper clean procedures. Various levels of voiding are for
examples easily introduced into the copper. If possible, defects will be introduced into
some test vehicles at a level still considered acceptable for Sn/Pb applications and the
consequences tested for.
Test Board: The first Pb-Free test vehicle designed and produced to promote, enhance,
and evaluate the aforementioned failure mechanisms is referred to as the Lead Free
Test Board (LFTB-1). The Lead Free Test Board (LFTB-1) is a relatively thick (0.093”),
multilayer (12 layer), test vehicle designed specifically for use in evaluating robustness
and process sensitivity of various laminate and dielectric materials, thru hole and via
construction, surface patterns, and State-of-the-Art component attachment sites. The
design incorporates unique test structures that provide visual, mechanical, chemical,
electrical and physical evaluation sites, defining data collection and yielding assignment
of overall board performance. Ultimately, the data generated from this test board will
provide design, construction, and performance information as well as baseline reliability
data for lead free assembly.
The functional design of this board was developed by Universal Instruments SMT Lab
as a collaborative assortment of project specific issues and requests submitted by
numerous Area Array 2004 Consortium members with regards to lead free assembly.
As the understanding of material failure mechanisms improves, and the availability of
planned production circuits dwindles, it was deemed necessary to pursue all potential
sources for acquisition of “live” product through consortium membership contributions.
Many member companies have submitted product for lead free evaluations (multiple
reflows, thermal analysis, thermal shock, material characterizations, and subsequent
microsectional analysis). Significant data has been collected to date, from these
contributions, which has yielded an overall indication of specific material survivability
and robustness in Pb-Free applications. Conversely, there have been contributions
which represent current material selections that do not survive lead free temperature
excursion. To date we have tested 9 resin systems on 20 different supplier’s materials.
In addition to live product submissions, UIC SMT Lab has been asked to participate in
external Design of Experiments (DOE’s) where varied lead free, certified ROHS, and
certified lead free PCB materials are being used to produce boards which can survive
the now famous 260°C Peak Reflow or NEMI profile. We are currently involved with a
Material Test Vehicle (MATV) that was designed by Sanmina-SCI, yet includes many of
the test structures and component attach sites originally designed into the LFTB-1. We
are working with 0.180” thick, 32 layer product and a thinner 0.093”, 16 layer product.
Initial evaluations of some Phenolic cured epoxy systems have revealed considerably
less robustness than initially promised in sales literature.
Components: It is as said critical that parts of the test board be populated with
especially selected components. It is proposed that these include a press fit connector
offered by Ericsson, as well as possibly one of the compliant pin connectors suggested
by IBM (Amp z-Pak, FCI AirMax, Teradyne VHDM, Tyco HM-Zd)? In addition, we
propose to include a DIP16 and some large through-hole mounted package such as a
power transformer on a wave-soldering coupon.
As far as surface mounted components we propose to include 2512s, a 1064 I/O area
array flip chip, and the 256 I/O BGA which we have already seen to damage some
boards in no-Pb assembly. In addition, we propose to include a relatively rigid large
BGA such as a 35mm package with a 22-23mm chip inside. If possible, commercial
samples of this may be procured, but we also propose to build our own generic BGA
with the same footprint and daisy chaining. This allows the daisy-chain to bypass the
chip and thus not risk internal package failure in testing, but even more importantly is
allows the production of vehicles with specifically desired thermomechanical properties.
In general, the surface mounted components should be placed as near as possible to
and/or over realistic via chains to assess their effects of damage to these. At least one
of the large BGA’s should also be attached to via-in-pad structures as this may seriously
affect local loads on these.
Characterization
Test vehicles will of course be characterized when initially received. Properties of
interest include stiffness and Coefficient of Thermal Expansion (CTE) versus
temperature, particularly in the thickness (z-expansion) direction. We shall also
measure properties such as glass transition and decomposition/degradation
temperatures. In general, we shall also quantify the as-received response of samples to
the relevant tests below for comparison with the same after preconditioning.
Preconditioning (Damage)
Preconditioning procedures that will be considered for potential damage to the boards
include the following.
One or several cycles of humidity/moisture exposure (such as 100%R.H. for 48 hours,
or a week at 50C/80%R.H.) and bake-out (such as 125C for 48hrs). A single cycle is
probably the most realistic as far as preconditioning before assembly is concerned.
Some samples should also be exposed to longer-term storage ‘on the shelf’.
We may also consider intermediate humidity/bake out cycles after first assembly steps,
but before wave soldering for example. Certainly, humidity exposure and aging after
final assembly will be included as an important preconditioning step.
Complete preconditioning will of course include realistic mass reflows followed by wave
soldering, perhaps selective soldering, and repair. Parameters and combinations will be
varied to help understand the effects of the individual ones on damage. Mass reflow
profiles will include peak temperatures of 220C (for reference), 260C and 275C (it may
be unrealistic to always count on temperatures remaining below this). Both short (45
sec above liquidus) and long (180 sec) profiles with and without a soak will be
considered as well. Effects of single as well as five and ten repeated reflows will be
assessed. Reflows will include actual component attachment whenever relevant.
Preheat and solder bath temperatures, as well as other wave soldering parameters, will
also be varied, and in this case the presence of the components is known to be critical.
Press fit and compliant pin connectors will be inserted at the appropriate point.
Aggressive cleaning may contribute strongly to the further degradation of damaged
boards.
Manual repair with a handheld point-soldering tool may in fact be the most damaging of
them all, but repairs with both a Metcal tool and a semi-automatic rework station with
various nozzles will be considered.
Importantly, as said, subsequent humidity exposure and aging ‘on the shelf’ and in
service may contribute strongly to degradation of boards initially (but undetectably)
damaged in reflow. This may happen before or after handling in shipment and/or a final
repair. Different sequences of repair, mechanical stressing, and moisture exposure will
therefore be included as well.
TESTS/RESPONSE PARAMETERS
Damage will be assessed in terms of directly detectable issues and reduced
performance or failure in various tests. The latter would include some of the current
tests referred to above, such as liquid-to-liquid thermal shock, air-to-air thermal cycling
and IST. Directly detectable would, among others, be a reduced Tg, enhanced moisture
absorption, or degradation in dielectric constant or loss, as well as visible or measurable
delamination or warpage. We would expect the time to delamination at 260C and 288C
to degrade, but in itself, this is not an indication of a problem. Emphasis will be on
damage of direct concern.
Board (solder mask) surfaces will be inspected for visual appearance, and samples will
obviously be cross-sectioned to inspect for IP separation and partial barrel cracks, etc.
Pieces will also be analyzed by TGA, DMA, and DSC for changes in resin properties.
Structures will be characterized in terms of insulation, etc. Initially invisible defects may,
however, only be detectable as leading to earlier failure in subsequent thermal cycling.
Whether this should be a real concern is easiest to assess for populated boards – the
board should never become the weakest link. Populated boards will therefore be cycled
thermally and/or mechanically (torque) or tested in mechanical shock (drop) or
deformation (bend).
Degradations in solder mask adhesion may be quantified in standard peel tests, but we
shall also test for solder penetration from exposed pads along covered traces. We shall
also test for adhesion of a typical die attach adhesive and a flip chip underfill to solder
mask and exposed laminate surfaces.
As far as contact pad adhesion is concerned, standard peel tests such as IPC-TM-650 -
2.4.8 are of little relevance, particularly for fine components. Degradation in adhesion,
particularly if enhanced by ambient exposure and aging, is likely to progress inwards
from the individual pad edges so that testing of a 32-125 mil wide strip will be insensitive
to preconditioning that may be fatal to a 3 mil wide trace. A more relevant test involving
solder attach to individual pads will therefore be developed and used.
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