5.3.7 What if multilayer PCBs are thought too costly?
In volume, four-layer PCBs now only cost between 20% and 50% more than two-layer. The use of planes usually turns out, in retrospect, to have been the most cost-effective EMC technique possible, especially when the overall financial break-even time and profitability of a product is considered.
An appropriate technique for low-density double-sided PCBs is to put all the tracks on one side, and a solid 0V plane on the other. For digital products, the lack of a power plane might require a number of ferrite beads in the power rails (see later), so it might not prove to be most cost-effective.
Where tracks must use both sides of a two-layer PCB, some EMC improvements may be had by "gridding" 0V tracks. This can be done by using a "maximum copper" or "area fill" on the 0V tracks of both PCB layers, which must run perpendicular to each other, "stitching" the resulting horizontal and vertical 0V areas and lines together with via holes wherever they cross to create a grid over the whole PCB area. Smaller grid sections are needed around the more sensitive or aggressive components, often difficult to achieve for leaded microprocessors but easier for SMD types. Time should be allowed for moving components and tracks around to achieve the best grid structure, but any grid will always be much less effective than a proper solid plane.
Single-sided PCBs are extremely difficult to make EMC compliant without enclosure shielding and filtering, except for circuits which naturally have very low emissions (low dV/dt and dI/dt) and also have naturally very high immunity (e.g. high signal levels and low impedances).

5.4 Power decoupling
The aim of power decoupling is to maintain the power supply impedance to each IC at 1Ω or less across the entire frequency range of interest (at least 150kHz to 1GHz for EMC). Some devices may need 0.1Ω or less over some frequency ranges for correct operation. Wires and PCB tracks have too much inductance to provide these low impedances, which require local capacitance of suitable quality and great attention to detail in PCB layout to minimise inductances.
Another aim is to reduce the size of the current loops in the power distribution, to reduce the emissions form this source. Happily, this is accomplished by the same techniques that lower the power supply impedance.

5.4.1 Power decoupling techniques
A large decoupling capacitor (typically 100μF, might be larger for power-hungry circuits) should be fitted where power supplies enter or leave a PCB, and some smaller ones (e.g. 10mF) should be ‘sprinkled’ around the PCB on a "μF per unit area" principle, as well as being positioned near to heavy power usage such as microprocessors, memory, and other powerful digital ICs. Using electrolytic technology these ‘bulk’ capacitors can provide a low impedance to about 3MHz.
Recently, several manufacturers have added high-capacitance multilayer ceramic capacitors to their surface-mounted product ranges. These are smaller or less costly or have lower ESR and/or better high frequency performance than electrolytics (such as solid tantalum), often several of these attributes at once. They also don’t suffer from reverse polarity or dV/dt problems, so should improve yields and reliability).
Next, the power supplies to every IC should be decoupled very nearby using appropriate capacitor sizes and types. Where an IC has a number of power pins, each pin should have an appropriate decoupling capacitor nearby, even if they are on the same supply (e.g. Vdd).
Achieving good decoupling above 10MHz gets more difficult as frequency increases, because the inductance of component leads, PCB tracks, via holes, and capacitor self-inductance, inevitably limit their performance. The achievement of good power supply decoupling at higher frequencies using capacitors mounted close to IC power pins is discussed next.
The total local decoupling capacitance required depends on the IC’s transient power demands and the tolerances of its DC power rails. VLSI and RAM manufacturers should be able to specify the values (and maybe even the capacitor types and preferred layout patterns) for their products, but note that they will probably have assumed an accurate 5V power supply – usually not true of real life.
The formula C(ΔV) = I(Δt), using the units Farads, Volts, Amps, and seconds, covers what we want to know. ΔV is obtained by subtracting the IC's minimum operational voltage (from its data sheet) from the worst-case minimum power rail voltage (taking account of initial tolerances, regulation, temperature coefficients, ageing drift, and the voltage drops in the power conductors). ΔV often turns out to be a mere +100mV. I is the IC's transient current demand from its power rail, which lasts for Δt. I and Δt are almost never found in data sheets, and must be measured in some reasonably sensible way with an oscilloscope. An obvious component of I is the device’s output (load) current, but this is often negligible in comparison with “shoot-through" currents, also known as “transient supply current”. There is no point in measuring I or Δt with greater than ±20% accuracy.
Where ΔV is low it may be cost-effective to increase it by improving the regulation of the power supply, and/or reducing the resistance of the power rails, rather than fit larger capacitors with their lower performance at high frequencies. This is a common argument for local power regulation.

5.4.2 Self-resonance problems
Self-resonance in capacitors stops them providing low impedances at high frequencies, with higher values generally being worse. The first self-resonant frequency (SRF) of a
capacitor is a series resonance, and a rule of thumb for this is: , where L = ESL (internal to the capacitor) + the total inductance of any leads + the total inductance of any tracks and/or vias. 1nH/mm may be assumed for leads and/or tracks from a capacitor to the power pins of its IC. The inductance contributed by 0V and power planes may be neglected when the capacitor is near to its IC. Decoupling capacitors generally become ineffective at more than 3 times their SRF, as shown by Figure 5D.

5.3.7 What if multilayer PCBs are thought too costly?
In volume, four-layer PCBs now only cost between 20% and 50% more than two-layer. The use of planes usually turns out, in retrospect, to have been the most cost-effective EMC technique possible, especially when the overall financial break-even time and profitability of a product is considered.
An appropriate technique for low-density double-sided PCBs is to put all the tracks on one side, and a solid 0V plane on the other. For digital products, the lack of a power plane might require a number of ferrite beads in the power rails (see later), so it might not prove to be most cost-effective.
Where tracks must use both sides of a two-layer PCB, some EMC improvements may be had by "gridding" 0V tracks. This can be done by using a "maximum copper" or "area fill" on the 0V tracks of both PCB layers, which must run perpendicular to each other, "stitching" the resulting horizontal and vertical 0V areas and lines together with via holes wherever they cross to create a grid over the whole PCB area. Smaller grid sections are needed around the more sensitive or aggressive components, often difficult to achieve for leaded microprocessors but easier for SMD types. Time should be allowed for moving components and tracks around to achieve the best grid structure, but any grid will always be much less effective than a proper solid plane.
Single-sided PCBs are extremely difficult to make EMC compliant without enclosure shielding and filtering, except for circuits which naturally have very low emissions (low dV/dt and dI/dt) and also have naturally very high immunity (e.g. high signal levels and low impedances).

5.4 Power decoupling
The aim of power decoupling is to maintain the power supply impedance to each IC at 1Ω or less across the entire frequency range of interest (at least 150kHz to 1GHz for EMC). Some devices may need 0.1Ω or less over some frequency ranges for correct operation. Wires and PCB tracks have too much inductance to provide these low impedances, which require local capacitance of suitable quality and great attention to detail in PCB layout to minimise inductances.
Another aim is to reduce the size of the current loops in the power distribution, to reduce the emissions form this source. Happily, this is accomplished by the same techniques that lower the power supply impedance.

5.4.1 Power decoupling techniques
A large decoupling capacitor (typically 100μF, might be larger for power-hungry circuits) should be fitted where power supplies enter or leave a PCB, and some smaller ones (e.g. 10mF) should be ‘sprinkled’ around the PCB on a "μF per unit area" principle, as well as being positioned near to heavy power usage such as microprocessors, memory, and other powerful digital ICs. Using electrolytic technology these ‘bulk’ capacitors can provide a low impedance to about 3MHz.
Recently, several manufacturers have added high-capacitance multilayer ceramic capacitors to their surface-mounted product ranges. These are smaller or less costly or have lower ESR and/or better high frequency performance than electrolytics (such as solid tantalum), often several of these attributes at once. They also don’t suffer from reverse polarity or dV/dt problems, so should improve yields and reliability).
Next, the power supplies to every IC should be decoupled very nearby using appropriate capacitor sizes and types. Where an IC has a number of power pins, each pin should have an appropriate decoupling capacitor nearby, even if they are on the same supply (e.g. Vdd).
Achieving good decoupling above 10MHz gets more difficult as frequency increases, because the inductance of component leads, PCB tracks, via holes, and capacitor self-inductance, inevitably limit their performance. The achievement of good power supply decoupling at higher frequencies using capacitors mounted close to IC power pins is discussed next.
The total local decoupling capacitance required depends on the IC’s transient power demands and the tolerances of its DC power rails. VLSI and RAM manufacturers should be able to specify the values (and maybe even the capacitor types and preferred layout patterns) for their products, but note that they will probably have assumed an accurate 5V power supply – usually not true of real life.
The formula C(ΔV) = I(Δt), using the units Farads, Volts, Amps, and seconds, covers what we want to know. ΔV is obtained by subtracting the IC's minimum operational voltage (from its data sheet) from the worst-case minimum power rail voltage (taking account of initial tolerances, regulation, temperature coefficients, ageing drift, and the voltage drops in the power conductors). ΔV often turns out to be a mere +100mV. I is the IC's transient current demand from its power rail, which lasts for Δt. I and Δt are almost never found in data sheets, and must be measured in some reasonably sensible way with an oscilloscope. An obvious component of I is the device’s output (load) current, but this is often negligible in comparison with “shoot-through" currents, also known as “transient supply current”. There is no point in measuring I or Δt with greater than ±20% accuracy.
Where ΔV is low it may be cost-effective to increase it by improving the regulation of the power supply, and/or reducing the resistance of the power rails, rather than fit larger capacitors with their lower performance at high frequencies. This is a common argument for local power regulation.

5.4.2 Self-resonance problems
Self-resonance in capacitors stops them providing low impedances at high frequencies, with higher values generally being worse. The first self-resonant frequency (SRF) of a
capacitor is a series resonance, and a rule of thumb for this is: , where L = ESL (internal to the capacitor) + the total inductance of any leads + the total inductance of any tracks and/or vias. 1nH/mm may be assumed for leads and/or tracks from a capacitor to the power pins of its IC. The inductance contributed by 0V and power planes may be neglected when the capacitor is near to its IC. Decoupling capacitors generally become ineffective at more than 3 times their SRF, as shown by Figure 5D.