As ever-evolving IC packages and multigigahertz signals present new pc-board design challenges, version 15.2 of Cadence's Allegro system interconnect design platform takes them on. With features that shorten the pc-board design cycle and enhance designer productivity, Allegro offers collaborative design benefits as well as novel library data-management functions.
New constraints across Allegro platform tools account for critical signal delays inherent in IC packages and vias. These constraints eliminate the need for designers to link to the package database or manually account for these delays. What results is more flexibility and increased design accuracy.
Key to the latest Allegro release is Allegro Design Entry HDL, which provides front-end support for creation and simulation of equivalent extended nets in design entry. Design Entry HDL boosts productivity through improved page-management operations and enhanced constraint application across signal nets.
The new release of Allegro also rolls out new features and technologies for the platform's PCB Editor, PCB SI, and Constraint Manager tools. The Allegro PCB Editor adds undo/redo capability and interactive etch-tuning functions that provide real-time feedback. Allegro PCB SI brings ease-of-use enhancements, support for IBIS 4.0 modeling, integration with a 3Dfield solver for package design, and support for new rules that can shorten post-layout verification time. The Allegro Constraint Manager boosts productivity with a new properties worksheet and usability improvements. |
