technologies for system-in-a-package and hybrid system-on-chip

Packaging and interconnection of integrated circuits are an increasingly important part of advanced microelectronic systems. These technologies have traditionally evolved at a much slower pace than the semiconductor technologies, creating a technology gap. New concepts and technologies are therefore required.

IMEC's research strategy on advanced device interconnect and packaging is primarily driven by the requirements set forward by both the semiconductor technology roadmap and the miniaturisation of electronic systems, in particular those need for ambient intelligence applications.

By adopting and “IC-centric” approach to packaging, it is possible to have “early insight” into packaging issues of the future IC generations. Furthermore, the use of “up-scaled” semiconductor technologies (multilayer thin film technology) allows IMEC to propose a unique solution for the packaging “interconnect-gap” and leverage the available knowledge of semiconductor processing technology to the packaging field.

The second driver for IMEC's packaging technology comes from the systems oriented work at IMEC. By closely collaborating, the system requirements may be translates into specific packaging requirements, which are an excellent guidance for the system-oriented packaging research (SiP), aimed at miniaturising systems and integrating RF-functionalities in the packaging levels. The M4 and the Human++ programs are examples of drivers for packaging development.

The main package and interconnect challenges addressed by APIC are:

• The acceleration of interconnect scaling to keep up with microelectronic scaling: the interconnect gap

• Integration of passive components in the interconnect and packaging technologies

• Heat removal from the components to the package, the board and, finally, the environment

• Chip/package co-design

• Miniaturization: ultra-thin, low profile/low volume solutions

• Environmental friendly packaging solutions: Pb-free/halogen free

• Cost-effective solutions

These challenges are studied in APIC's focussed research areas:

RF-SiP and Heterogeneous RF-wafer-level packaging (WLP) Integration

• Above-IC integration of RF-passives (see section Above-IC technology )

• Multilayer thin-film technology (see section Multilayer thin film)

• RF-MEMS integration (see section RF-MEMS and RF-MEMS packaging)

• RF wireless system integration (see section RF wireless system modules)

3D integration

• 3D-SiP: SiP interposer/package level 3D interposer (see section 3D Systems in a package (SiP))

• 3D-WLP: post-passivation 3D Si-vias (see section 3D-WLP: stacked ICs), die-to-wafer or wafer-to-wafer micro-bump bonding (see section Micro-bumping), and chip embedding techniques. (see section 3D-WLP: Ultra-thin-chip stacking (UTCS))

• 3D-tacked IC: post front-end-of-line Cu-nail 3D Si-vias, high density die-to-wafer bonding (see section 3D-stacked ICs)

Wafer level packaging (see section Wafer-level packaging),

• Flip-chip scaling, flip chip interposers

• Wafer-level CSP - flexible assemblies

• Redistribution and above-IC copper technology

Thermal management (see section Thermal management),

Optical interconnect (see section Optical interconnect),

Advanced PCB and flex (see section Introduction on micro-systems integration), (see section Electrical interconnect), (see sectionFlexible and stretchable microsystems).

To achieve these goals, APIC is focusing on technologies that offer solutions at different levels of the interconnect hierarchy, using three main technology platforms: Multilayer thin film, advanced PCB and flex technology and advanced assembly technologies. This is illustrated schematically in figure1.

Figure 1: IMEC's interconnect and packaging technologies for bridging the interconnect gap between the IC and the PCB assembly level. Three main technology platforms are used: multilayer thin-film (yellow), advanced PCB and flex technology (green) and advanced assembly technologies (blue).

Packaging and interconnect research requires a “concurrent engineering” approach. It is highly interdisciplinary, requiring knowledge of technology, materials, thermal and mechanical properties, reliability, electrical characteristics and design methods as well as system and economic aspects. This is implemented in APIC, where different teams working on the technology platforms, reliability, thermal and mechanical analysis and electrical design and characterisation are strongly interacting, as shown in figure2.

Figure 2: Interactions between different competence teams and the technology platforms within APIC.

3D-system integration strategy

For the realization of highly miniaturized systems, a 3D-interconnect strategy is required. The 3D interconnects may be realized at different levels of the interconnect hierarchy. This results in different 3D-interconnect requirements and different technology solutions. C11639

In an attempt to categorize these technologies, one can start from the technology platform (“factory-type”) used to create the 3D interconnect structures. IMEC identifies 3 major technology platforms for 3D integration, based on the underlying infrastructure:

• 3D-SiP: packaging infrastructure

• 3D-WLP: wafer-level packaging infrastructure

• 3D-SIC: IC-foundry infrastructure

The 3D-SiP technology encompasses the packages with wire-bond die-stacks, but also involves package-on-package 3D stacks. It is currently the most mature technology and in high-volume production. A relatively low packaging density characterizes 3D-SiP.

The 3D-WLP technology is based on wafer-level packaging infrastructure, as used for flip chip bumping and redistribution metallizations. Using additional technology elements developed for MEMS-technology, such as deep anisotropic Si-etching, 3D electrical connections can be realized at the wafer level. This technology allows for higher integration densities than 3D-SIP. Characteristic for this technology is that 3D processing is performed after wafer-fabrication, “post-passivation”.

The 3D-SIC approach uses the Si-foundry technology to create very high density vertical interconnects. Many technologies are proposed in this area, but so far they are still in the R&D phase.

In figure3, a comparison of these different approaches is presented. A common aspect of all technologies is the need for die thinning technologies down to 50µm and less. A schematic representation of IMEC's R&D roadmap is given in figure4 .

Figure 3: Classification and comparison of different 3D interconnect technologies at different levels of the interconnect hierarchy.

Figure 4: IMEC´s 3D packaging and interconnection roadmap for 3D-SiP, 3D-WLP and 3D-SIC technology families