Field-programmable gate arrays (FPGAs) have proven a valuable technology, offering performance, time-to-market and cost advantages over application specific integrated circuits (ASICs). Today many circuit boards contain at least one FPGA. But does the placement process compromise those benefits? And what are the issues of FPGA-on-board integration, including independent FPGA and PCB design processes, high pin count packages, changing pin assignments, high-speed I/O and other factors?

Routing interconnect delays on the FPGA significantly affect the overall circuit performance and led to the development of physical FPGA synthesis tools. Routing interconnect delays on high-density PCBs significantly affect overall board performance and can compromise FPGA performance too. As such, a new approach is needed to solve this huge FPGA-on-board problem, and to handle easily the complexities of placing large, fast-edged FPGA devices on the PCB. These complexities can be broken down into connectivity and timing closure issues, and addressed with process integration for ease-of-use.

Often FPGAs--and, increasingly, PCBs--are designed by separate teams of designers. These design teams are quite different from each other and each has its own processes and requirements. FPGAs are primarily designed and described in a hardware description language (HDL), feeding downstream logic and physical synthesis steps. In contrast, PCB designs are still largely schematically based with no equivalent synthesis steps.

With the huge FPGA devices and packages now available (for example, the 1517-ball flip-chip BGA), it is imperative that basic connectivity data, pin data and status (locked or unlocked, and so on), can be passed easily between the diverse PCB and FPGA design processes. This information needs to be passed alongside key implementation constraints including part, speed-grade, I/O slew-rate and other buffering type constraints. Also, design changes made during the FPGA design process with the appropriate design checks need to be passed from the FPGA back to the PCB designers.

PCB librarians typically create component symbols to be used within the PCB schematic. These symbols are considered static and owned by the librarian. The large number of pins offered by the FPGA coupled with its programmability creates the need for a "custom" FPGA symbol. In many cases, the PCB logic designer chooses to create a custom symbol, so the pin names reflect the user-defined FPGA signal names for easy schematic wiring. Without these custom symbols, the PCB logic designer would be faced with connecting a signal "ABC" to "Bank_2_IOPAD_54"; a painful process when parts have in excess of 1000 pins. A custom symbol permits the PCB logic designer to wire pin "ABC" to signal "ABC." The custom symbol provides for a more expedient and less error-prone process. In addition.