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Some interface devices (such as some RS232 ICs) are claimed to withstand EN61000-4-2 testing directly on their RX and TX connections. But for the vast majority of semiconductors it is by far the best to protect them from the direct effects of ESD by using the dielectric isolation (insulation) or shielding techniques, described above.
But if for some reason circuit conductors really must be exposed to ESD sparks: using a series resistor or choke (as shown in Figure 6D) may allow the ESD injection into the circuit to be handled by an IC’s own internal protection devices. This is only likely to be possible for interface or ‘glue logic’ devices, and can’t be generally recommended for VLSI devices such as microprocessors not intended to connect directly to external cables.
Most resistors or chokes aren’t rated for ESD voltages, but may cope if they are physically large, have enough thermal inertia, and don’t arc-over themselves. Since there is very little energy in a personnel ESD event, a large thermal inertia will prevent the resistor from suffering damage, although the same may not be able to be said of some machine ESD events involving large stored charge. It may be necessary to put a number of resistors or ferrites in series so that they share the ESD voltage and don’t arc-over or break down (close to each other and arranged in a straight line, to get maximum advantage from this technique).
Since resistor and choke manufacturers don’t specify their products’ specifications on EN 61000-4-2 tests, it is best to check a few in a representative circuit and PCB layout. It may be found that different values may be needed for different ICs. The chokes used should be carefully chosen to provide a high impedance over the range of frequencies encompassed by the ESD event. Always perform a number of tests, to make sure that ‘soft’ failures aren’t happening.
Mask shrinks by semiconductor manufacturers can make such a protective circuit design inadequate (just as it can invalidate all other EMC measures), so it is always best to have an arrangement with your semiconductor suppliers that they will warn you in plenty of time of any impending mask shrinks, so you can purchase some buffer stock to continue production whilst you evaluate all the EMC effects of the mask shrink, including any ESD protection.
The resistors or chokes may need to have such high values that they prevent the circuit from operating correctly. This is a particular problem for high-speed signals. One solution is to add discrete transient voltage suppressers, as described later. These will handle much larger voltage and current transients than most devices’ internal protection measures, allowing series resistors or chokes to be reduced in impedance, or removed altogether.
However, a potentially serious problem for all methods that merely prevent fatal damage to semiconductors from direct ESD injection, is that they do not prevent momentary corruption of signals. Signal corruption can cause an ESD test to be failed, even though devices are undamaged. This is discussed later.
As asserted above, it is always best not to allow sparks to get into circuit conductors. But if, for some reason, circuit conductors really must be exposed to ESD sparks: it may be possible to arrange for the associated ICs to survive by fitting series resistors or chokes as described above. An alternative technique that is widely advertised by TVS manufacturers is to fit suitably-rated discrete TVSs between the vulnerable conductors and the local 0V plane, a shown in Figure 6D. Being very much higher rated than an IC’s internal protection devices, series resistance or chokes can have much lower impedance, and are often dispensed with altogether, which is sometimes much better for functionality.
Low inductance plane bonds are required for TVSs to protect ICs correctly, so the techniques described in Part 5 for connecting decoupling capacitors to 0V planes should be followed. Also, the PCB track to be protected must pass through the other terminal of the TVS. ‘Spurring’ a track from the signal path to a nearby TVS creates inductance which can prevent the TVS from protecting the IC. Since the TVS is required to bypass the powerful discharge current from the signal conductor into its local 0V plane, care must be taken that the ESD transient discharge current – now flowing in the 0V circuit and looking for a route back to the external earth – does not cause problems elsewhere in the product.
TVS components are now available in a wide range of voltage and power ratings, in leaded and SMD styles. They are also available as space-saving PCB-mounted arrays, and also fitted into connectors where they shunt the spark current into the metal body of the connector (which therefore needs to have a good high-frequency bond to the metal enclosure or the PCB’s 0V plane). Some manufacturers make very thin flexible circuits which fit over the solder pins of common connector types, allowing an easy TVS retrofit to every pin of the connector.
A big advantage of discrete TVSs over filtering is that they do not compromise high-speed signals as much. Most of them are based on zener technology so they do have some capacitance, and for very high speed signals the choice of an adequately low-capacitance TVS which still has the desired ratings can still be quite limited. Where extremely low capacitance ESD protection is needed, reverse-biased diodes between the signal conductor and the 0V and power planes, as shown in Figure 6E, can be effective. Reverse-biased diodes have a significantly lower capacitance than zener diodes. The diodes need to be able to handle the ESD currents when forward-biased, and the local power plane needs sufficient high-frequency decoupling capacitance so that its voltage does not rise too much when it absorbs the ESD charge. Where the leakage currents of TVSs or diodes are the problem, rather than capacitance, it is possible to use FETs instead to get nanoamp leakage.
Unfortunately, although TVSs are often advertised as a complete solution to problems of EN 61000-4-2 ESD sparks getting into exposed circuitry, this is not the case in practice. Their problem, which they share with the ICs internal protection devices and the reverse-biased diodes above, is that they cannot prevent the ESD transient from corrupting the signals on the conductors they are protecting.
Techniques additional to the use of TVSs are thus required to prevent signal corruption, and these are described in a later section.
Following a series resistor or choke with a capacitor to the local 0V plane (as shown by Figure 6F) can provide excellent protection from direct ESD injection to a conductor. As well as helping prevent actual damage, it can reduce transient voltages to such low levels that excessive signal corruption is prevented. Unfortunately, this approach has its limitations for high-speed signals.
The capacitor in the circuit shares the charge with the capacitance in the source of the ESD event. Since the source of a personnel ESD event has a capacitance of 150pF (although some older human-body models used by older test standards use 330pF) a 1nF capacitor in the circuit would reduce an 8kV voltage to about 1000V, 10nF would reduce it to about 120V, and 100nF would reduce it to about 12V.
Adding a series impedance such as a resistor or choke between the ESD event and the capacitor reduces the peak currents, which if left unchecked could be tens of amps and could physically overstress the capacitor and might also cause secondary problems due to the intense magnetic fields resulting. A 1kW series resistor would limit the peak current of an 8kV discharge to 8A, 10kW to 800mA, and 100kW to 80mA.
So we can see that a 100kW resistor followed by a 100nF capacitor would tame a personnel ESD event very considerably, where the wanted signals concerned were slow enough not to mind a filter with a 1 second time-constant. Of course, the series resistor or choke would need to be able to withstand 8kV without damage, and this rules out the use of ordinary resistors (unless a number are used in series). Surge-rated resistors are available, but they are larger and more expensive than ordinary resistors. Some manufacturers of ferrite beads test their products to check that they are not damaged when ESD events of up to 25kV are applied across them, but I am not sure whether they allow them to flash-over during the test. Surface-mounted resistors and ferrite beads may be relied upon to flash-over at quite low voltages, due to the small spacings between their terminations. Unfortunately a number of SMDs in series may not voltage-share very well due to variations in surface contamination, so when using this technique rather than a guaranteed non-flash-over (probably leaded) component – it may be best to design-in a very large margin (e.g. use twice as many components in series as appears necessary).
When the load impedance is much greater than the series impedance in the protection circuit, the high voltages due to the ESD event can last a long time and the protection is achieved by charge balancing and peak current limitation. But when the load impedance of the IC or circuit to be protected is much lower than the impedance of the series resistor of ferrite in the RC circuit, the ESD event lasts a much short time and so the RC circuit also acts as a low-pass filter, giving even greater attenuation of the ESD event and hence greater protection.
Applying the ‘low-pass filter’ protection circuit after a TVS (as shown in figure 6E) can be useful where load impedances are less than the impedance of the series element (resistor or ferrite choke): the TVS reduces the ESD’s 8kV (or whatever) to a few tens of volts, and the low-pass filter then attenuates it to less than the desired level. Of course, the peak currents into the TVS will be very large (unless limited by a series resistor) and these may cause problems due to their local magnetic fields, but the resistor or ferrite choke following the TVS will not have to be rated for the ESD voltage and can be an ordinary component.
Where fast signals are involved, filtering on individual lines may not be able to achieve useful ESD protection without negatively affecting the wanted signal, although common-mode filtering may well be possible (see later). Transient voltage suppressers may need to be used instead (see above), since they add only little capacitive loading, along with communication protocols or software techniques (see below), but it is still best not to let the spark get into the conductors in the first place.
Because external signal and power cables are initially at their previous voltages, a ‘ground lift’ event due to a metal enclosure being struck by an ESD spark makes a transient high voltage appear across circuitry which interfaces with external cables.
All things being relative, it is as if the enclosure was at earth potential and all its external cables had been suddenly raised to a high voltage. For example, if an enclosure was suddenly charged to +4kV by an ESD spark, it is as if the enclosure remained at earth potential but all the external cables had been suddenly charged to -4kV instead.
Although filters and/or TVSs may be used on each individual power or signal line, to help protect the electronics interfacing with the external cables (as described in the previous two sections), filtering each signal line independently is usually not compatible with high-speed signals, whereas TVSs can’t prevent signal corruption (see later).
Because the transient voltage experienced by the interface circuitry is identical for all the conductors in a given cable it is a common-mode (CM) transient, and CM suppression techniques may be used to help suppress the transient voltage without compromising high-speed signals.
Figure 6G shows a common-mode choke used for this purpose. It needs as many windings as there are conductors in the cable. Surface-mounted and leaded common-mode chokes are available with up to eight windings. If the CM choke has a high enough value of common-mode impedance over the frequencies of concern it may be able to prevent an ESD transient from damaging the interface electronics. In situations where signal corruption is the problem, a CM choke can greatly reduce the signal perturbation.
When a CM choke is used with filter capacitors even greater suppression can be achieved, although this is not as suitable for high-speed signals unless quite small capacitor values are used (say between 10pF and 1nF, depending on the application).
Where a large number of conductors must be accommodated specially-wound chokes may be required. A favourite technique is to pass the cable through a soft-ferrite cylinder or toroid. A single pass through a typical 32mm long ferrite cylinder creates a common-mode impedance of around 250W at 100MHz, not as much as some PCB-mounted components, but often enough to make a useful improvement to an EMC problem.
Where higher common-mode impedance is required, two or more turns of the cable could be made through the ferrite, to increase the impedance. Unfortunately, multiple turns also reduces the frequency at which the peak impedance is achieved, so beyond a certain number of turns no further benefit (at a given frequency) may be achieved by adding more turns. We would normally expect that the impedance presented by a choke would increase according to the square of the number of turns, but this is not always the case for soft ferrites, as shown by the following example (kindly provided by Alan Keenan of Steward Inc.). Tests on a particular soft-ferrite core found that with two turns its Z peaked at 692W at 322MHz; with three turns its Z peaked higher at 809W but at the lower frequency of 152MHz; and with four turns wound on it - its Z peaked even higher at 1300W but at the even lower frequency of 108MHz.
Multiple ferrites strung along a cable increase impedance proportionally to the number of ferrites, without reducing the frequency of the impedance peak, but can look a bit Heath-Robinson. Cables passed through ferrites should always finish on the other side of the ferrite from the side they entered, so that the ferrites are like beads strung on a length of string, for best high-frequency performance. Any stray capacitance from one end of the ferrite (or chain of ferrites) to the other will compromise the high-frequency performance, making the routing of the cable or track very important.
Galvanically isolated external connections help a great deal with making products immune to ESD (and also to conducted transients and surges). PCB-mounted opto-isolators and transformers may be used, although many types will not have sufficient creepage and clearance and voltage withstand for ESD, and many types will have internal parasitic capacitances which may allow excessive transient currents to flow. Isolating mains transformers that meet their appropriate safety standards often seem quite adequate for protecting power supplies from personnel ESD, despite their shortcomings as ESD barriers.
The very best galvanic isolation for external signal communications is achieved with fibre-optic, wireless, or infra-red techniques, since these do not involve any conductors with dissimilar voltages being anywhere near the product concerned. Of course, the transmitting and receiving modules concerned can be very sensitive, and are often best fitted with their own local shielding, but even quite large PCB-mounted shields are now available taped and reeled for automatic placement and so can be much more cost-effective than when such items required manual assembly. Fibre optic cables sometimes use metal strengtheners, armour, or metal vapour barriers, and these can compromise the creepage and clearance distances required for ESD protection so should be stripped well back from any connections with products, where it is not possible to avoid the use of such cables entirely.
Five years ago I began expressing the opinion that by 2005 people who used copper cables to connect signals between items of equipment would be thought rather old-fashioned, and I still believe that this timescale is correct.
When ESD testing to harmonised EMC standards using the EN 61000-4-2 test method, it is normal for the requirement to be that the operational state of the product being tested (and its displays and stored data) is exactly the same after the test as before. This is usually also the case for other transient tests such as Fast Transient Bursts (EN 61000-4-4), Surge (EN 61000-4-5), and the various automotive transients described by ISO 7637.
Using an IC’s internal protection or a TVS to protect against ESD (or other types of conducted transient or surge) does nothing to prevent signal or data corruption, and can result in the product’s operational state, displays, or memory being different after the test, leading to test failure. Additional techniques are often needed to prevent signal corruption.
For ordinary control lines such as keyboards, ‘debouncing’ techniques (whether hardware or software, such as are routinely used to debounce mechanical contacts) can work very well. Low-pass filtering (see above) is a good old-fashioned ‘debouncing’ technique often used after a TVS.
High-speed data can’t use powerful debouncing techniques, and some type of error-protecting protocol is usually required, although of course this slows down the data rate too.
Where a single ESD event causes a single bit error in a serial communication, the use of simple parity check or Hamming coding can make a big improvement in immunity. However, these techniques will be less effective when the interference comes in bursts, as is usual for non-ESD transients, or when an ESD event causes secondary arcing. Some very comprehensive error-correcting protocols are now commercially available (see section 1.4.7), and it is usually much more cost-effective and time-saving to purchase the necessary chips or software licenses than it is to try to develop your own protocols. Unlike simple techniques such as parity checking or Hamming coding most such protocols have a high resistance for burst errors, and have been field proven in a wide range of applications and situations.
Momentary corruption of analogue signals is sometimes acceptable, when all that results is a brief click in a headphone or momentary flicker of a meter needle. But where decision thresholds may be crossed, or where the analogue signal is put through an averaging routine or stored in a memory after digitisation, even a brief error in an analogue signal may be unacceptable.
Since analogue signals can’t easily use error-correcting protocols, debouncing techniques (such as a low-pass filter) are often used. Where the analogue signal must use high frequencies, it becomes very difficult to filter the transient event from the signal, the more so as the accuracy required (equivalent to number of bits of resolution) is increased, so dielectric isolation or shielding techniques are necessary after all, to prevent the ESD transient from getting into the signal conductor.
According to some experts, the effects of poor supply quality on electronic equipment is one of the most significant causes of downtime and financial loss world-wide. Dips, sags, brownouts, swells, voltage variations, dropouts and interruptions are the main causes of poor supply quality. (In some areas waveform distortion is also becoming an important issue.)
EN 61000-4-11 is the basic test standard for dips, sags, brownouts, swells, voltage variations, dropouts and interruptions in the AC mains supply, but is not harmonised under the EMC directive so cannot be used when self-declaring conformity to standards. For self-declaration to standards it is necessary to use the harmonised generic or product standards - which now generally call-up the use of EN 61000-4-11 as the basic test method. It is always the generic or product standards that set the actual test limits, and they are often a lot less comprehensive than the limits in EN 61000-4-11.
When using the Technical Construction File route to conformity it is often permissible to use EN 61000-4-11 directly.
Of course there is no reason why a manufacturer should not apply EN 61000-4-11 to a product in any case, in addition to the requirements of any harmonised product or generic standards, and this may sometimes discover reliability problems with products that would otherwise have been overlooked.
Dips are short-term reductions in supply voltage caused by load switching and fault clearance in the AC supply network. They can also be caused by switching between the mains and alternative supplies in uninterruptible power supplies or emergency power back-up systems. Examples of dips: 30% dip for 10ms, 60% dip for 100ms. Figure 6H shows a 40% dip for 20ms (one mains cycle). A dip of 40% is equivalent to a reduction in supply voltage to 60% of its nominal value.
EN / IEC 61000-4-11 refers to a Unipede study of dips which covered public mains supplies.
Dip depth Number of dips/yr with given durations
10-100ms 100-500ms 0.5-1s 1-3s
10-30% 61 66 12 6
30-60% 8 36 4 1
60-100% 2 17 3 2
Dips may not occur in isolation - sometimes a fast sequence of dips occurs. Most immunity tests apply dips abruptly, starting and finishing at a zero crossing, but in practice they can have gentle rates of change and start and stop at any point in the mains cycle.
EN61000-4-11 recommends testing with 30% and 60% dips (70% and 40% of nominal voltage respectively) for 0.5, 1, 5, 10, 25 and 50 cycles of the supply waveform in each case. Although the generic immunity standard for domestic, commercial, and light industrial environments EN 50082-1:1997 (which will be replaced by EN 61000-6-1 sometime around 2004) uses EN 61000-4-11 as its basic test method, it merely requires testing with 30% dips for 10ms and 60% dips for 100ms.
Likewise, EN 61000-6-2:1999 (which replaces EN 50082-2:1995 in April 2002) also uses EN 61000-4-11 as its basic test method but only requires testing with 30% dips for 10ms, 60% dips for 100ms and 1 second. Many of the other harmonised standards under the EMC and RTTE directives specify dip test % and durations which are different from the above generics and from each other, and which are not as comprehensive as EN 61000-4-11.
Because no high frequencies are involved it is fairly easy to construct your own supply dips tester using a pair of solid-state zero-crossing relays, a variable transformer and a timing generator, as shown by Figure 6J. Safety issues must not be neglected ! A test laboratory would be more likely to use a programmable mains synthesiser with enough short-term capacity to handle the product’s inrush current. |
